TC3404 Datasheet, PDF(4/16 Page) Microchip Technology – +1.8V Low Power, Quad Input, 16-Bit Sigma-Delta A/D Converter with a Power Fault Monitor

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TC3404 Datasheet, PDF (4/16 Pages) Microchip Technology – +1.8V Low Power, Quad Input, 16-Bit Sigma-Delta A/D Converter with a Power Fault Monitor

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TC3404

TC3404 DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: TA = 25Â°C and VDD = 2.7V, unless otherwise specified. Boldface type specifications apply for

temperatures of 0Â°C to 85Â°C. VREF = 1.25V, Internal Clock Frequency = 520kHz.

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

SCLK, A0, A1, ENABLE

VIL

VIH

ILEAK

Input Low Voltage

Input High Voltage

Leakage Current

SDAT, PFO

VOL

VOH

VDDMIN

PFI

Output Low Voltage

Output High Voltage (SDAT)

Minimum VDD for PFO Valid

0.7 x VDD

0.3 x VDD

ÂµA

0.9 x VDD

1.1

0.4

V IOL = 1.5mA

V ISOURCE = 400ÂµA (Note 3)

1.3

ÂµA

VCCPFI

PFI Input Voltage Range

PFI Input Current

-0.1

VTHR

Threshold (VTH, PFI)

Threshold Hysteresis

Threshold Tempco

Note 1: Differential input voltage defined as (VIN+ â VIN-).

2: Resistance from INn+ to INn- or INn to GND.

3: @ VDD = 1.8V, ISOURCE â¤ 200ÂµA.

.01

1.23

VDD

0.1

ÂµA

ppm/Â°C

TC3404 AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: TA = 25Â°C and VDD = 2.7V, unless otherwise specified. Boldface type specifications apply for

temperatures of 0Â°C to 85Â°C. VREF = 1.25V, Internal Clock Frequency = 520kHz.

Symbol

Parameter

Min

Typ

Max Unit

Test Conditions

Resolution Reduction Clock Width

Âµsec Width of SCLK (Negative)

Resolution Reduction Clock Width

Âµsec Width of SCLK (Positive)

Conversion Time (15-bit Plus Sign) â

125

msec 16-bit Conversion, TA = 25Â°C (Note 1)

Conversion Time (14-bit Plus Sign) â

t3/2.0

msec 15-bit Conversion

Conversion Time (13-bit Plus Sign) â

t3/4.0

msec 14-bit Conversion

Conversion Time (12-bit Plus Sign) â

t3/7.8

msec 13-bit Conversion

Conversion Time (11-bit Plus Sign) â

t3/15.1

msec 12-bit Conversion

Conversion Time (10-bit Plus Sign) â

t3/28.6

msec 11-bit Conversion

Conversion Time (9-bit Plus Sign)

t3/51.4

msec 10-bit Conversion

Resolution Reduction Window

t3/85.7

msec Width of SCLK

SCLK to Data Valid

1000

nsec SCLK Falling Edge to SDAT Valid

Address Setup

nsec Address Valid to SCLK

Address Hold

1000

nsec SCLK to Address Valid Hold

Acknowledge Delay

1000 nsec SCLK to SDAT Delay

t11

RESET Delay

Âµsec Delay VTH Falling at 10V/msec to

RESET Low

Note 1: Nominal temperature drift is -2830ppm/CÂ° for temperature less than 25Â°C and -1340ppm/Â°C for temperatures

greater than 25Â°C.

DS21413B-page 4

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