TC1225 Datasheet, PDF (4/10 Pages) Microchip Technology – Inverting Dual (-VIN, -2VIN) Charge Pump Voltage Converters

TC1225
TC1226
TC1227
The internal switch resistance for the first stage (i.e.
R_SWITCH1) is approximately 3Ω and the switch resistance for
the second stage (i.e. R_SWITCH2) is approximately 7Ω.
The losses in the circuit due to factor (4) above are also
shown in Equation 2a for stage 1 and Equation 2b for stage
2. The output voltage ripple for stage 1 is given by Equation
3a and the output voltage ripple for stage 2 is given by
Equation 3b.
P_{LOSS1 (4)} = [ (0.5)(C1)(V_IN ² – V_OUT12 ) + (0.5)
(C_OUT1) (V_RIPPLE12 - 2V_OUT1 V_RIPPLE1) ] x f_OSC
Equation 2a.
P_{LOSS2 (4)} = [ (0.5) (C2) (V_IN ² – V_OUT22 ) + (0.5)
(C_OUT2) (V_RIPPLE22 - 2V_OUT2 V_RIPPLE2) ] x f_OSC
Equation 2b.
V_RIPPLE1 = [ I_OUT1 / (f_OSC) (C_OUT1) ] + 2 (I_OUT1)
(ESR_COUT1)
Equation 3a.
V_RIPPLE2 = [ I_OUT2 / (f_OSC) (C_OUT2) ] + 2 (I_OUT2)
(ESR_COUT2)
Equation 3b.
Capacitor Selection
In order to maintain the lowest output resistance and
output ripple voltage, it is recommended that low ESR
capacitors be used. Additionally, larger values of C1 and C2
will lower the output resistance and larger values of C_OUT1
and C_OUT2 will reduce output ripple. (See Equations 1a, 1b,
3a, and 3b). NOTE: For proper charge pump operation,
C1 and C_OUT1 must have a voltage rating greater than or
equal to V_IN, while C2 and C_OUT2 must have a voltage
rating greater than or equal to 2V_IN.
Table 1a shows various values of C1 and the corre-
sponding output resistance values for V_IN=5V @ +25°C for
stage 1 and Table 1b shows various values of C2 and the
corresponding output resistance values for V_IN=5V @ +25°C
for stage 2. It assumes a 0.1Ω ESR_C1, a 0.1Ω ESR_C2, a 3Ω
R_SWITCH1, and a 7Ω R_SWITCH2.
Table 2a shows the output voltage ripple for various
Inverting Dual (–V_IN, –2V_IN)
Charge Pump Voltage Converters
values of C_OUT1 and Table 2b shows the output voltage
ripple for various values of C_OUT2 (again assuming V_IN=5V
@ +25^oC). The V_RIPPLE1 values assume a 3mA output load
current for stage 1 and a 0.1Ω ESR_COUT1. The V_RIPPLE2
values assume a 200uA output load current for stage 2 and
a 0.1Ω ESR_COUT1.
Table 1a. Output Resistance vs. C1 (ESR = 0.1Ω). For Stage 1
C1 (µF) TC1225 R_OUT (Ω) TC1226 R_OUT (Ω) TC1227 R_OUT (Ω)
0.47
202
85
42
1
108
53
33
3.3
50
33
27
Table 1b. Output Resistance vs. C2 (ESR = 0.1Ω). For Stage 2
C2 (µF) TC1225 R_OUT (Ω) TC1226 R_OUT (Ω) TC1227 R_OUT (Ω)
0.1
890
342
137
0.47
239
117
74
1
140
85
65
Table 2a. Output Voltage Ripple vs. C_OUT1 (ESR = 0.1Ω) For Stage 1
(I_OUT1 = 3mA)
C_OUT1
(µF)
TC1225 V_RIPPLE1 TC1226 V_RIPPLE1
(mV)
(mV)
TC1227 V_RIPPLE1
(mV)
0.47
533
183
52
1
251
86
25
3.3
76
27
8
Table 2b. Output Voltage Ripple vs. C_OUT2 (ESR = 0.1Ω) For Stage 2
(I_OUT2 = 200µA)
C_OUT2
(µF)
TC1225 V_RIPPLE2
(mV)
TC1226 V_RIPPLE2
(mV)
TC1227 V_RIPPLE2
(mV)
0.1
167
57
16
0.47
36
12
3.4
1
17
5.8
1.6
Input Supply Bypassing
TheV_IN input should be capacitively bypassed to reduce
AC impedance and minimize noise effects due to the switch-
ing internal to the device. It is recommended that a large
value capacitor (at least equal to C1) be connected from V_IN
to GND for optimal circuit performance.
TC1225/6/7-1 3/24/00
4
© 2001 Microchip Technology Inc. DS21369A