DSPIC30F5011_11 Datasheet, PDF (37/220 Pages) Microchip Technology – High-Performance 16-bit Digital Signal Controllers

4.2 Reset Sequence
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
4.2.1 RESET SOURCES
In addition to external Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an address pointer will cause a Reset.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
dsPIC30F5011/5013
4.3 Traps
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 4-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note:
If the user does not intend to take correc-
tive action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and sets the
IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
4.3.1 TRAP SOURCES
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The Math Error trap executes under the following four
circumstances:
• If an attempt is made to divide by zero, the divide
operation will be aborted on a cycle boundary and
the trap taken
• If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A or
B causes an overflow from bit 31 and the accumu-
lator guard bits are not utilized
• If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A or
B causes a catastrophic overflow from bit 39 and
all saturation is disabled
• If the shift amount specified in a shift instruction is
greater than the maximum allowed shift amount, a
trap will occur
© 2011 Microchip Technology Inc.
DS70116J-page 37