MCP2030A Datasheet, PDF (36/74 Pages) Microchip Technology – Three-Channel Analog Front-End Devicewith 1 mVPP Input Detection Sensitivity

MCP2030A
5.7 Fixed Gain Amplifiers 1 and 2
FGA1 and FGA2 provide a maximum two-stage gain of
40 dB.
Note: The user cannot control the gain of these
two amplifiers.
5.8 Auto-Channel Selection
The auto-channel selection feature is enabled if the
Auto-Channel Select bit AUTOCHSEL<8> in Configu-
ration Register 5 (Register 5-6) is set, and disabled if
the bit is cleared. When this feature is active (i.e.,
AUTOCHSE <8> = 1), the control circuit checks the
demodulator output of each input channel immediately
after the AGC settling time (T_STAB). If the output is high,
it allows this channel to p ass data, otherwise it i s
blocked.
The status of this operation is monitored by Status Reg-
ister 7 bits <8:6> (Register 5-8). These bits indicate the
current status of th e channel selection activity, and
automatically updates for every Soft Reset period. The
auto-channel selection function resets after each Soft
Reset (or after Inactivity Timer time-out). Therefore, the
blocked channels are re-enabled after Soft Reset.
This feature can make the output signal cleaner by
blocking any channel that was not high at the en d of
T_AGC. This function works only for demodulated data
output, and is not a pplied for c arrier clock or R SSI
output.
5.9 Carrier Clock Detector
The Carrier Clock Detector senses the input carrier
cycles. The output of the detector switches digitally at
the signal carrier frequency. Carrier clock output is
available when the output is selected by the DATOUT
bit in Configuration Register 1 (Register 5-2).
5.10 Demodulator
The Demodulator consists of a full-wave rectifier, low-
pass filter, peak detector and Data Slicer that detects
the envelope of the input signal.
5.11 Data Slicer
The Data Slicer consists of a reference generator and
comparator. The Data Slicer compares the input with
the reference voltage. The re ference voltage comes
from the minimum modulation depth requirement set-
ting and input peak voltage. The data from all 3 chan-
nels are ORed together and sent to the output-enable
filter.
5.12 Output-Enable Filter
The output-enable filter enables the LFDATA output
once the incoming signal meets the wake-up sequence
requirements (see Section 5.15 “Configurable
Output-Enable Filter”).
5.13 Received Signal Strength
Indicator (RSSI)
The RSSI provides a current which is proportional to
the input signal amplitude (see Section 5.30.3
“Received Signal Strength Indicator (RSSI)
Output”).
5.14 Analog Front-End Timers
The device has an internal 32 kHz RC oscillator. The
oscillator is used in several timers:
• Inactivity Timer
• Alarm Timer
• Pulse Width Timer
• Period Timer
• AGC Settling Timer
5.14.1 RC OSCILLATOR
The RC oscillator generates a 32 kHz internal clock.
5.14.2 INACTIVITY TIMER
The Inactivity Timer is used to automatically return the
device to Standby mode, if there is no input signal. The
time-out period is approximately 16 ms (T_INACT), based
on the 32 kHz internal clock.
The purpose of the Inactivity Timer is to minimize cur-
rent draw by automatically returning to the lower cur-
rent Standby mode if, for the T_INACT period, there is not
an input signal.
The timer is reset when:
• An amplitude change occurs in LF input signal,
either from high-to-low or low-to-high
• the CS pin is low (any SPI command)
• a timer-related Soft Reset occurs
The timer starts after the AGC initialization period of
time (T_AGC).
The timer causes a Sof t Reset when, for the T_INACT
period, a pre viously-received input signal does not
change from either high-to-low or low-to-high.
The Soft Reset returns the device to Standby mode,
where most of the analog circuits, such as the AGC,
demodulator, and RC oscillator, are powered down.
This returns the device to the lower Standby Current
mode.
DS22235B-page 36
 2011 Microchip Technology Inc.