PIC16F1825-I-ST Datasheet, PDF (35/418 Pages) Microchip Technology – 14/20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1825/1829
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 2
100h⁽¹⁾ INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
101h⁽¹⁾ INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
102h⁽¹⁾ PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
103h⁽¹⁾ STATUS
—
—
—
TO
PD
Z
DC
C
---1 1000 ---q quuu
104h⁽¹⁾ FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
105h⁽¹⁾ FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
106h⁽¹⁾ FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
107h⁽¹⁾ FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
108h⁽¹⁾ BSR
—
—
—
BSR<4:0>
---0 0000 ---0 0000
109h⁽¹⁾ WREG
Working Register
0000 0000 uuuu uuuu
10Ah⁽¹⁾ PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
10Bh⁽¹⁾ INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF 0000 0000 0000 0000
10Ch LATA
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0 --xx -xxx --uu -uuu
10Dh LATB⁽²⁾
LATB7
LATB6
LATB5
LATB4
—
—
—
—
xxxx ---- xxxx ----
10Eh LATC
LATC7⁽²⁾ LATC6⁽²⁾
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 xxxx xxxx uuuu uuuu
10Fh —
Unimplemented
—
—
110h
—
Unimplemented
—
—
111h
CM1CON0
C1ON
C1OUT
C1OE
C1POL
—
C1SP
C1HYS C1SYNC 0000 -100 0000 -100
112h
CM1CON1
C1INTP
C1INTN
C1PCH<1:0>
—
—
C1NCH1 C1NCH0 0000 ---0 0000 ---0
113h
CM2CON0
C2ON
C2OUT
C2OE
C2POL
—
C2SP
C2HYS C2SYNC 0000 -100 0000 -100
114h
CM2CON1
C2INTP
C2INTN
C2PCH<1:0>
—
—
C2NCH<1:0>
0000 --00 0000 --00
115h
CMOUT
—
—
—
—
—
—
MC2OUT MC1OUT ---- --00 ---- --00
116h
BORCON
SBOREN
—
—
—
—
—
—
BORRDY 1--- ---q u--- ---u
117h
FVRCON
FVREN FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
0q00 0000 0q00 0000
118h
DACCON0
DACEN
DACLPS
DACOE
—
DACPSS<1:0>
—
DACNSS 000- 00-0 000- 00-0
119h
DACCON1
—
—
—
DACR<4:0>
---0 0000 ---0 0000
11Ah SRCON0
SRLEN
SRCLK<2:0>
SRQEN SRNQEN SRPS
SRPR 0000 0000 0000 0000
11Bh SRCON1
SRSPE
SRSCKE SRSC2E⁽²⁾ SRSC1E
SRRPE SRRCKE SRRC2E⁽²⁾ SRRC1E 0000 0000 0000 0000
11Ch —
Unimplemented
—
—
11Dh APFCON0
RXDTSEL SDOSEL⁽³⁾ SSSEL⁽³⁾
—
T1GSEL TXCKSEL
—
—
000- 0000 000- 0000
11Eh APFCON1
—
—
SDO2SEL⁽²⁾ SS2SEL⁽²⁾ P1DSEL P1CSEL P2BSEL CCP2SEL --00 0000 --00 0000
11Fh —
Unimplemented
—
—
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
PIC16(L)F1829 only.
PIC16(L)F1825 only.
 2010-2011 Microchip Technology Inc.
Preliminary
DS41440B-page 35