DSPIC30F2023-30I-PT Datasheet, PDF (35/286 Pages) Microchip Technology – 28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers

FIGURE 3-5:
dsPIC30F1010/202X
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
15
EA<15> = 0
Data
Space
EA
16
15
EA<15> = 1
Data Space
0x0000
PSVPAG⁽¹⁾
0x00
8
Program Space
0x8000
Address
23
15
15 Concatenation 23
0x100100
0
0x001200
Upper half of Data
Space is mapped
into Program Space
0xFFFF
0x001FFE
BSET
MOV
MOV
MOV
CORCON,#2
#0x00, W0
W0, PSVPAG
0x9200, W0
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
3.2 Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1 DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
256 byte data address space (including all Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 256 bytes data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y
address space from data space and address it using
EAs sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
A data space memory map is shown in Figure 3-6.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 33