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PIC18LF2455-I Datasheet, PDF (343/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology | |||
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PIC18F2455/2550/4455/4550
NEGF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Negate f
NEGF f {,a}
0 ⤠f ⤠255
a â [0,1]
(f) + 1 â f
N, OV, C, DC, Z
0110 110a ffff ffff
Location âfâ is negated using twoâs
complement. The result is placed in the
data memory location âfâ.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank (default).
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ⤠95 (5Fh). See
Section 26.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write
register âfâ
Example:
NEGF REG, 1
Before Instruction
REG =
After Instruction
REG =
0011 1010 [3Ah]
1100 0110 [C6h]
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No Operation
NOP
None
No operation
None
0000 0000
1111 xxxx
No operation.
1
1
0000
xxxx
0000
xxxx
Q2
No
operation
Q3
No
operation
Q4
No
operation
Example:
None.
© 2009 Microchip Technology Inc.
DS39632E-page 341
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