PIC16C6X_13 Datasheet, PDF (33/334 Pages) Microchip Technology – null8-Bit CMOS Microcontrollers

PIC16C6X
TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets⁽³⁾
Bank 1
80h⁽¹⁾ INDF
81h
OPTION
82h⁽¹⁾ PCL
83h⁽¹⁾ STATUS
84h⁽¹⁾ FSR
85h
TRISA
86h
TRISB
87h
TRISC
88h⁽⁵⁾ TRISD
89h⁽⁵⁾ TRISE
8Ah^(1,2) PCLATH
8Bh⁽¹⁾ INTCON
8Ch
PIE1
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
—
—
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
PORTD Data Direction Register
1111 1111 1111 1111
IBF
OBF
IBOV PSPMODE
—
PORTE Data Direction Bits
0000 -111 0000 -111
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
PSPIE⁽⁶⁾
(4)
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
8Eh
PCON
—
—
—
—
—
8Fh
—
Unimplemented
90h
—
Unimplemented
91h
—
Unimplemented
92h
PR2
Timer2 Period Register
93h
SSPADD Synchronous Serial Port (I²C mode) Address Register
94h
SSPSTAT
SMP
CKE
D/A
P
S
95h
—
Unimplemented
96h
—
Unimplemented
97h
—
Unimplemented
—
—
CCP2IE ---- ---0 ---- ---0
—
POR
BOR ---- --qq ---- --uu
—
—
—
—
—
—
1111 1111 1111 1111
0000 0000 0000 0000
R/W
UA
BF
0000 0000 0000 0000
—
—
—
—
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
9Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.
 1997-2013 Microchip Technology Inc.
DS30234E-page 33