MCP8025 Datasheet, PDF (33/64 Pages) Microchip Technology – 3-Phase Brushless DC (BLDC) Motor Gate Driver with Power Module, Sleep Mode, and LIN Transceiver

4.3.4
EXTERNAL DRIVE FOR A 3-PHASE
BRIDGE WITH NMOS/NMOS
MOSFET PAIRS
Each motor phase is driven with external
NMOS/NMOS MOSFET pairs. These are controlled by
a low-side and a high-side gate driver. The gate drivers
are controlled directly by the digital input pins
PWM[1:3]H/L. A logic high turns the associated gate
driver ON and a logic low turns the associated gate
driver OFF. The PWM[1:3]H/L digital inputs are
equipped with internal pull-down resistors.
The low-side gate drivers are biased by the +12V LDO
output, referenced to ground. The high-side gate
drivers are a floating drive biased by a bootstrap
capacitor circuit. The bootstrap capacitor is charged by
the +12V LDO whenever the accompanying low-side
MOSFET is turned on.
The high-side and low-side driver outputs all go to a low
state whenever there is a fault or when CE = 0,
regardless of the PWM[1:3]H/L inputs.
4.3.4.1
MOSFET Driver External Protection
Features
Each driver is equipped with Undervoltage Lockout
(UVLO) and short-circuit protection features.
4.3.4.1.1 MOSFET Driver Undervoltage Lockout
(UVLO)
The MOSFET UVLO fault detection monitors the
available voltage used to drive the external MOSFET
gates. The fault detection is only active while the driver
is actively driving the external MOSFET gate. Anytime
the driver bias voltage is below the Driver Undervoltage
Lockout (D_UVLO) threshold for a period longer than the
one specified by the t_DUVLO parameter, the driver will
not turn on when commanded ON. A driver fault will be
indicated to the host microcontroller on the
ILIMIT_OUT open-drain output pin and also via a DE2
communication STATUS_1 message. This is a latched
fault. Clearing the fault requires either removal of
device power or disabling and re-enabling the device
via the device enable input (CE). The EXTUVLO bit in
the CFG0 register is used to enable or disable the
Driver Undervoltage Lockout feature. This protection
feature prevents the external MOSFETs from being
controlled with a gate voltage not suitable to fully
enhance the device.
MCP8025/6
4.3.4.1.2 External MOSFET Short-Circuit Current
Short-circuit protection monitors the voltage across the
external MOSFETs during an ON condition. The
high-side driver voltage is measured from VDD to
PH[1:3]. The low-side driver voltage is measured from
PH[1:3] to PGND. If the voltage rises above a
user-configurable threshold after the external MOSFET
gate voltage has been driven high, all drivers will be
turned OFF. A driver fault will be indicated to the host
microcontroller on the open-drain ILIMIT_OUT output
pin and also via a DE2 communication STATUS_1
message. This is a latched fault. Clearing the fault
requires either removal of device power or disabling
and re-enabling the device via the device enable input
(CE). This protection feature helps detect internal
motor failures such as winding to case shorts.
Note:
The driver short-circuit protection is
dependent on application parameters. A
configuration message is provided for a
set number of threshold levels. The
MOSFET Driver UVLO and short-circuit
protection features have the option to be
disabled.
The short-circuit voltage may be set via a DE2
SET_CFG_0 message. The EXTOC<1:0> bits in the
CFG0 register are used to select the voltage level for
the short-circuit comparison. If the voltage across the
MOSFET drain-source terminals exceeds the selected
voltage level when the MOSFET is active, a fault will be
triggered. The selectable voltage levels are 250 mV,
500 mV, 750 mV and 1000 mV. The EXTSC bit in the
CFG0 register is used to enable or disable the
MOSFET driver short-circuit detection.
4.3.4.1.3 Fault Pin Output (ILIMIT_OUT)
The dual-purpose ILIMIT_OUT pin is used as a fault
indicator and as an overcurrent indicator when used
with the internal DAC. The pin is capable of sinking a
minimum of 1 mA of current while maintaining less than
50 mV of voltage across the output. An external pull-up
resistor to the logic supply is required.
The open-drain ILIMIT_OUT pin transitions low when a
fault occurs. Table 4-4 lists the faults that activate the
ILIMIT_OUT signal. Warnings do not activate the
ILIMIT_OUT signal. Table 4-5 lists the warnings.
 2016 Microchip Technology Inc.
DS20005339B-page 33