MCP3911 Datasheet, PDF (33/72 Pages) Microchip Technology – 3.3V Two-Channel Analog Front Endx1null

5.3.4
AUTOZEROING FREQUENCY
SETTING (AZ_FREQ)
The MCP3911 modulators include an autozeroing algo-
rithm to improve the offset error performance and
greatly diminish 1/f noise in the ADC. This algorithm
permits it to reach very high SNR and flattens the noise
spectrum at the output of the ADC (see performance
graphs Figure 2-1, Figure 2-2, Figure 2-3 and Figure 2-
4). This autozeroing algorithm is performed synchro-
nously with the MCLK coming to the device, and its rate
can be adjusted throughout the AZ_FREQ bit in the
CONFIG register.
When AZ_FREQ=0 (default) the autozeroing is hap-
pening at the slowest rate, which diminishes the 1/f
noise while not impacting the THD performance. This
mode is recommended for low values of the PGA gain
(GAIN=1x or 2x).
When AZ_FREQ=1, the autozeroing is happening at
the fastest rate, which further diminishes the 1/f noise
and further improves the SNR, especially at higher gain
settings. The THD may slightly be impacted in this
mode (see Figure 2-22). This mode is recommended
for higher PGA gain settings to improve SNR (GAIN
superior or equal to 4x).
5.3.5 DITHER SETTINGS
Both modulators also include a dithering algorithm that
can be enabled through the DITHER<1:0> bits in the
configuration register. This dithering process improves
THD and SFDR (for high OSR settings) while
increasing slightly the noise floor of the ADCs. For
power metering applications and applications that are
distortion-sensitive, it is recommended to keep
DITHER at maximum settings for best THD and SFDR
performance. In the case of power metering applica-
tions, THD and SFDR are critical specifications. Opti-
mizing SNR (noise floor) is not really problematic due
to large averaging factor at the output of the ADCs,
therefore even for low OSR settings, the dithering algo-
rithm will show a positive impact on the performance of
the application.
MCP3911
5.4 Modulator Output Block
If the user wishes to use the modulator output of the
device, the appropriate bits to enable the modulator
output must be set in the configuration register.
When MODOUT<1:0> bits are enabled, the modulator
output of the corresponding channel is present at the
corresponding MDAT output pin as soon as the
command is placed. Additionally, the corresponding
SINC filter is disabled in order to consume less current.
The corresponding DR pulse is also not present at the
DR output pin. When MODOUT<1:0> bits are cleared,
the corresponding SINC filters are back to normal oper-
ation and the corresponding MDAT outputs are in high
impedance.
Since the Delta-Sigma modulators have a 5-level out-
put given by the state of four comparators with ther-
mometer coding, their outputs can be represented on
four bits, each bit giving the state of the corresponding
comparator (See Table 5-3). These bits are present on
the MOD register and are updated at the DMCLK rate.
In order to output the comparators result on a separate
pin (MDAT0 and MDAT1), these comparator output bits
have been arranged to be serially output at the AMCLK
rate (See Figure 5-2).
This 1-bit serial bitstream is the same that would be
produced by a 1-bit DAC modulator with a sampling
frequency of AMCLK. The modulator can either be
considered like a 5 level-output at DMCLK rate, or 1-bit
output at AMCLK rate. These two representations are
interchangeable. The MDAT outputs can therefore be
used in any application that requires 1-bit modulator
outputs. These applications will often integrate and
filter the 1-bit output with SINC, or more complex
decimation filters computed by a MCU or a DSP.
TABLE 5-3: DELTA-SIGMA MODULATOR
CODING
Comp<3:0>
Code
Modulator
Output Code
MDAT Serial
Stream
1111
+2
0111
+1
0011
0
0001
-1
0000
-2
1111
0111
0011
0001
0000
© 2012 Microchip Technology Inc.
DS22286A-page 33