PIC12F1516 Datasheet, PDF (31/344 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

TABLE 3-5: PIC16(L)F1518/9 MEMORY MAP (CONTINUED)
400h
40Bh
40Ch
41Fh
420h
46Fh
470h
47Fh
BANK 8
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
480h
48Bh
48Ch
49Fh
4A0h
4EFh
4F0h
4FFh
BANK 9
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
500h
50Bh
50Ch
51Fh
520h
56Fh
570h
57Fh
BANK 10
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
580h
58Bh
58Ch
59Fh
5A0h
5EFh
5F0h
5FFh
BANK 11
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
BANK 12
600h
60Bh
60Ch
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
680h
68Bh
68Ch
61Fh
620h
64Fh
General Purpose
Register
48 Bytes
69Fh
6A0h
650h
66Fh
670h
67Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
6EFh
6F0h
6FFh
BANK 13
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
700h
70Bh
70Ch
71Fh
720h
76Fh
770h
77Fh
BANK 14
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
780h
78Bh
78Ch
79Fh
7A0h
7EFh
7F0h
7FFh
BANK 15
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
800h
80Bh
80Ch
86Fh
870h
87Fh
BANK 16
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
880h
88Bh
88Ch
8EFh
8F0h
8FFh
BANK 17
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
900h
90Bh
90Ch
96Fh
970h
97Fh
BANK 18
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
980h
98Bh
98Ch
9EFh
9F0h
9FFh
BANK 19
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A00h
A0Bh
A0Ch
A6Fh
A70h
A7Fh
BANK 20
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A80h
A8Bh
A8Ch
AEFh
AF0h
AFFh
BANK 21
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
B00h
B0Bh
B0Ch
B6Fh
B70h
B7Fh
BANK 22
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
B80h
B8Bh
B8Ch
BEFh
BF0h
BFFh
BANK 23
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)