MCP3914 Datasheet, PDF (31/80 Pages) Microchip Technology – 3V Eight-Channel Analog Front End

5.3.4 DITHER SETTINGS
All modulators include a dithering algorithm that can be
enabled through the DITHER<1:0> bits in the
Configuration register. This dithering process improves
THD and SFDR (for high OSR settings), while slightly
increasing the noise floor of the ADCs. For power
metering applications and applications that are
distortion sensitive, it is recommended to keep DITHER
at maximum settings for best THD and SFDR
performance. In the case of power metering
applications, THD and SFDR are critical specifications.
Optimizing SNR (noise floor) is not problematic due to
the large averaging factor at the output of the ADCs.
Therefore, even for low OSR settings, the dithering
algorithm will show a positive impact on the
performance of the application.
MCP3914
5.4 SINC³ + SINC¹ Filter
The decimation filter present in all channels of the
MCP3914 is a cascade of two sinc filters (sinc³+sinc¹):
a third order sinc filter with a decimation ratio of OSR₃,
followed by a first order sinc filter with a decimation
ratio of OSR₁ (moving average of OSR₁ values).
Figure 5-2 represents the decimation filter architecture.
Modulator
Output
4
SINC³
OSR₁=1
SINC¹
OSR₃
OSR₁
Decimation
Filter Output
16 (WIDTH=0)
24 (WIDTH=1)
Decimation Filter
FIGURE 5-2:
MCP3914 Decimation Filter Block Diagram.
Equation 5-1 calculates the filter z-domain transfer
function.
EQUATION 5-1: SINC FILTER TRANSFER
FUNCTION
Hz
=


1
–
-
z
OSR3_ ³

---------------------------------------------



1
–
-
z
OSR1

OS
R3_

--------------------------------------------------------
OSR31 – z^–1³
OSR1

 ¹
–
-
z
OS
R3_

Where z = EXP2  j  f_in  DMCLK
Equation 5-2 calculates the settling time of the ADC as
a function of DMCLK periods.
The SINC¹ filter following the SINC³ filter is only
enabled for the high OSR settings (OSR > 512). This
SINC¹ filter provides additional rejection at a low cost
with little modification to the -3 dB bandwidth. The
resolution (number of possible output codes expressed
in powers of two or in bits) of the digital filter is 24-bit
maximum for any OSR and data format choice. The
resolution depends only on the OSR<2:0> settings in
the CONFIG0 register per the Table 5-3. Once the OSR
is chosen, the resolution is fixed and the output code
respects the data format defined by the
WIDTH_DATA<1:0> setting in the STATUSCOM
register (see Section 5.5 “ADC Output Coding”).
EQUATION 5-2:
SettlingTimeDMCLKperiods=3  OSR3 + OSR1 – 1  OSR3
 2013 Microchip Technology Inc.
DS20005216A-page 31