MCP3910 Datasheet, PDF (31/86 Pages) Microchip Technology – 3V Two-Channel Analog Front End

5.0 DEVICE OVERVIEW
5.1 Analog Inputs (CHn+/-)
The MCP3910 analog inputs can be connected directly
to current and voltage transducers (such as shunts,
current transformers or Rogowski coils). Each input pin
is protected by specialized ESD structures that allow
bipolar ±2V continuous voltage, with respect to A_GND,
to be present at their inputs without the risk of perma-
nent damage.
All channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin relative to A_GND should be maintained in the ±1V
range during operation in order to ensure the specified
ADC accuracy. The common mode signals should be
adapted to respect both the previous conditions and
the differential input voltage range. For best
performance, the common mode signals should be
maintained to A_GND.
Note:
If the analog inputs are held to a potential
of -0.6 to -1V for extended periods of time,
MCLK must be present inside the device
in order to avoid large leakage currents at
the analog inputs. This is true even during
Hard Reset mode, or during the Soft
Reset of all ADCs. However, during the
Shutdown mode of all the ADCs or during
the POR state, the clock is not distributed
inside the circuit. During these states, it is
recommended to keep the analog input
voltages above -0.6V referred to A_GND, to
avoid high analog inputs leakage currents.
5.2 Programmable Gain Amplifiers
(PGA)
The Programmable Gain Amplifiers (PGAs) reside at
the front-end of each delta-sigma ADC. They have two
functions: translate the common-mode voltage of the
input from A_GND to an internal level between A_GND and
AV_DD, and amplify the input differential signal. The
translation of the common-mode voltage does not
change the differential signal, but recenters the com-
mon-mode so that the input signal can be properly
amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the delta-sigma
modulator must not be exceeded. The PGA for
Channel n is controlled by the PGA_CHn<2:0> bits in
the GAIN register. Table 5-1 displays the gain settings
for the PGA.
MCP3910
TABLE 5-1: PGA CONFIGURATION
SETTING
Gain
Gain Gain
PGA_CHn<2:0> (V/V) (dB)
V_IN Range (V)
0 00
1
0 01
2
0 10
4
0 11
8
1 0 0 16
1 0 1 32
0 ±0.6
6 ±0.3
12 ±0.15
18 ±0.075
24 ±0.0375
30 ±0.01875
Note: The two undefined settings are G = 1. This
table is defined with V_REF = 1.2V.
5.3 Delta-Sigma Modulator
5.3.1 ARCHITECTURE
All ADCs are identical in the MCP3910, and they
include a proprietary second-order modulator with a
multi-bit 5-level DAC architecture (see Figure 5-1). The
quantizer is a flash ADC composed of four comparators
with equally spaced thresholds and a thermometer
output coding. The proprietary 5-level architecture
ensures minimum quantization noise at the outputs of
the modulators without disturbing linearity or inducing
additional distortion. The sampling frequency is
DMCLK (typically 1 MHz with MCLK = 4 MHz) so the
modulators are refreshed at a DMCLK rate.
Figure 5-1 represents a simplified block diagram of the
delta-sigma ADC present on MCP3910.
Differential
Voltage Input
Loop
Filter
Second-
Order
Integrator
Quantizer
5-level
Flash ADC
Output
Bitstream
DAC
MCP3910 Delta-Sigma Modulator
FIGURE 5-1:
Block Diagram.
Simplified Delta-Sigma ADC
 2012-2014 Microchip Technology Inc.
DS20005116B-page 31