PIC16F84A_07 Datasheet, PDF (30/88 Pages) Microchip Technology – 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller

PIC16F84A
FIGURE 6-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD):
SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
TPWRT
TOST
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
6.7 Time-out Sequence and
Power-down Status Bits (TO/PD)
On power-up (Figures 6-6 through 6-9), the time-out
sequence is as follows:
1. PWRT time-out is invoked after a POR has
expired.
2. Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and PWRTE configuration bit status. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
TABLE 6-5: TIME-OUT IN VARIOUS
SITUATIONS
Oscillator
Configuration
Power-up
PWRT PWRT
Enabled Disabled
XT, HS, LP
RC
72 ms +
1024TOSC
1024TOSC
72 ms
—
Wake-up
from
SLEEP
1024TOSC
—
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high, execution will begin immediately
(Figure 6-6). This is useful for testing purposes or to
synchronize more than one PIC16F84A device when
operating in parallel.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the RESET conditions for some special
registers, while Table 6-4 lists the RESET conditions
for all the registers.
TABLE 6-6: STATUS BITS AND THEIR
SIGNIFICANCE
TO PD
Condition
1 1 Power-on Reset
0 x Illegal, TO is set on POR
x 0 Illegal, PD is set on POR
0 1 WDT Reset (during normal operation)
0 0 WDT Wake-up
1 1 MCLR during normal operation
1 0 MCLR during SLEEP or interrupt
wake-up from SLEEP
DS35007B-page 28
© 2001 Microchip Technology Inc.