TC4469COE713 Datasheet, PDF (3/22 Pages) Microchip Technology – Logic-Input CMOS Quad Drivers

TC4467/TC4468/TC4469
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage ...............................................................+20 V
Input Voltage ............................. (GND – 5 V) to (V_DD + 0.3 V)
Package Power Dissipation: (T_A ≤ 70°C)
PDIP...................................................................800 mW
CERDIP .............................................................840 mW
SOIC ..................................................................760 mW
Package Thermal Resistance:
CERDIP R_θJ-A ...................................................100°C/W
CERDIP R_θJ-C.....................................................23°C/W
PDIP R_θJ-A ..........................................................80°C/W
PDIP R_θJ-C ..........................................................35°C/W
SOIC R_θJ-A ..........................................................95°C/W
SOIC R_θJ-C..........................................................28°C/W
Operating Temperature Range:
C Version ................................................... 0°C to +70°C
E Version.................................................-40°C to +85°C
M Version ..............................................-55°C to +125°C
Maximum Chip Temperature ....................................... +150°C
Storage Temperature Range.........................-65°C to +150°C
†Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, T_A = +25°C, with 4.5 V ≤ V_DD ≤ 18 V.
Parameters
Sym
Min
Typ Max Units
Conditions
Input
Logic 1, High Input Voltage
Logic 0, Low Input Voltage
Input Current
Output
V_IH
2.4
—
V_DD
V Note 3
V_IL
—
—
0.8
V Note 3
I_IN
-1.0
—
+1.0
µA 0 V ≤ V_IN ≤ V_DD
High Output Voltage
Low Output Voltage
Output Resistance
Peak Output Current
Continuous Output Current
V_OH V_DD – 0.025 —
V_OL
—
—
R_O
—
10
I_PK
—
1.2
I_DC
—
—
—
—
—
0.15
15
—
300
500
V I_LOAD = 100 µA (Note 1)
V I_LOAD = 10 mA (Note 1)
Ω I_OUT = 10 mA, V_DD = 18 V
A
mA Single Output
Total Package
Latch-Up Protection Withstand
I
—
500
—
mA 4.5 V ≤ V_DD ≤ 16 V
Reverse Current
Switching Time (Note 1)
Rise Time
Fall Time
Delay Time
Delay Time
Power Supply
t_R
—
15
25
nsec Figure 4-1
t_F
—
15
25
nsec Figure 4-1
t_D1
—
40
75
nsec Figure 4-1
t_D2
—
40
75
nsec Figure 4-1
Power Supply Current
I_S
—
1.5
4
mA
Power Supply Voltage
V_DD
4.5
—
18
V Note 2
Note 1: Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching
times are ensured by design.
2: When driving all four outputs simultaneously in the same direction, V_DD will be limited to 16 V. This reduces the chance that internal dv/dt
will cause high-power dissipation in the device.
3: The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 µsec
to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below
the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
 2002 Microchip Technology Inc.
DS21425B-page 3