TC1044S Datasheet, PDF (3/11 Pages) TelCom Semiconductor, Inc – CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER

Charge Pump DC-TO-DC Voltage Converter
TC1044S
Circuit Description
The TC1044S contains all the necessary circuitry to
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10 µF polar-
ized electrolytic capacitors. Operation is best understood by
considering Figure 2, which shows an idealized voltage
inverter. Capacitor C₁ is charged to a voltage, V⁺, for the half
cycle when switches S₁ and S₃ are closed. (Note: Switches
S₂ and S₄ are open during this half cycle.) During the second
half cycle of operation, switches S₂ and S₄ are closed, with
S₁ and S₃ open, thereby shifting capacitor C₁ negatively by
V⁺ volts. Charge is then transferred from C₁ to C₂, such that
the voltage on C₂ is exactly V⁺, assuming ideal switches and
no load on C₂.
The four switches in Figure 2 are MOS power switches;
S₁ is a P-channel device, and S₂, S₃ and S₄ are N-channel
devices. The main difficulty with this approach is that in
integrating the switches, the substrates of S₃ and S₄ must
always remain reverse-biased with respect to their sources,
but not so much as to degrade their ON resistances. In
addition, at circuit start-up, and under output short circuit
conditions (V_OUT = V⁺), the output voltage must be sensed
and the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and probable
device latch-up.
This problem is eliminated in the TC1044S by a logic
network which senses the output voltage (V_OUT) together
with the level translators, and switches the substrates of
S₃ and S₄ to the correct level to maintain necessary reverse
bias.
V+
C1 ⁺
1µF
1
8
2
7
TC1044S
3
6
4
5
IS
COSC*
V+
IL ^(+5V)
RL
V+
S1
GND _S3
S2
C1
C2
S4
VOUT = – VIN
Figure 2. Idealized Charge Pump Inverter
The voltage regulator portion of the TC1044S is an
integral part of the anti-latch-up circuitry. Its inherent voltage
drop can, however, degrade operation at low voltages. To
improve low-voltage operation, the “LV” pin should be
connected to GND, disabling the regulator. For supply
voltages greater than 3.5V, the LV terminal must be left
open to ensure latch-up-proof operation and prevent device
damage.
Theoretical Power Efficiency
Considerations
In theory, a capacitive charge pump can approach
100% efficiency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The TC1044S approaches these conditions for nega-
tive voltage multiplication if large values of C₁ and C₂ are
used. Energy is lost only in the transfer of charge
between capacitors if a change in voltage occurs. The
energy lost is defined by:
VOUT
E = 1/2 C₁ (V₁₂ – V₂₂)
C2
+ ^10µF
NOTE: For large values of C_OSC (>1000pF), the values
of C₁ and C₂ should be increased to 100µF.
Figure 1. TC1044S Test Circuit
© 2001 Microchip Technology Inc. DS21348A
V₁ and V₂ are the voltages on C₁ during the pump and
transfer cycles. If the impedances of C₁ and C₂ are relatively
high at the pump frequency (refer to Figure 2) compared to
the value of R_L, there will be a substantial difference in
voltages V₁ and V₂. Therefore, it is desirable not only to
make C₂ as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C₁ in order to achieve maximum efficiency of operation.
3
TC1044S-12 9/16/96