DSPIC30F6011A_06 Datasheet, PDF (3/238 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F6011A/6012A/6013A/6014A
dsPIC30F6011A/6012A/6013A/6014A High-Performance
Digital Signal Controllers
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• Flexible addressing modes
• 83 base instructions
• 24-bit wide instructions, 16-bit wide data path
• Up to 144 Kbytes on-chip Flash program space
• Up to 48K instruction words
• Up to 8 Kbytes of on-chip data RAM
• Up to 4 Kbytes of nonvolatile data EEPROM
• 16 x 16-bit working register array
• Up to 30 MIPS operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with PLL
active (4x, 8x, 16x)
• Up to 41 interrupt sources:
- 8 user-selectable priority levels
- 5 external interrupt sources
- 4 processor traps
DSP Features:
• Dual data fetch
• Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
• All DSP instructions are single cycle:
- Multiply-Accumulate (MAC) operation
• Single-cycle ±16 shift
Peripheral Features:
• High-current sink/source I/O pins: 25 mA/25 mA
• Five 16-bit timers/counters; optionally pair up
16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions:
• Data Converter Interface (DCI) supports common
audio Codec protocols, including I²S and AC’97
• 3-wire SPI modules (supports 4 Frame modes)
• I²C™ module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Two addressable UART modules with FIFO
buffers
• Two CAN bus modules compliant with CAN 2.0B
standard
Analog Features:
• 12-bit Analog-to-Digital Converter (ADC) with:
- 200 Ksps conversion rate
- Up to 16 input channels
- Conversion available during Sleep and Idle
• Programmable Low-Voltage Detection (PLVD)
• Programmable Brown-out Reset
Special Microcontroller Features:
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
• Data EEPROM memory:
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip
low-power RC oscillator for reliable operation
© 2006 Microchip Technology Inc.
Preliminary
DS70143C-page 1