24C08B Datasheet, PDF (3/12 Pages) Microchip Technology – 8K/16K 5.0V I 2 C O Serial EEPROMs

24C08B/16B
TABLE 1-3: AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Remarks
Clock frequency
FCLK
—
100
kHz
Clock high time
THIGH
4000
—
ns
Clock low time
TLOW
4700
—
ns
SDA and SCL rise time
TR
—
1000
ns
(Note1)
SDA and SCL fall time
TF
—
300
ns
(Note 1)
START condition hold time THD:STA
4000
—
ns
After this period the first clock
pulse is generated
START condition setup time TSU:STA
4700
—
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
—
ns
Data input setup time
TSU:DAT
250
—
ns
STOP condition setup time TSU:STO
4000
—
ns
Output valid from clock
TAA
—
3500
ns
(Note 2)
Bus free time
TBUF
4700
—
ns
Time the bus must be free before
a new transmission can start
Output fall time from VIH
TOF
min to VIL max
—
250
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppres-
TSP
sion (SDA and SCL pins)
—
50
ns
(Note 3)
Write cycle time
TWR
—
10
ms
Byte or Page mode
Endurance 24C08B
24C16B
—
1M
—
cycles 25°C, VCC = 5.0V, Block Mode
—
10M
—
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
SCL
TSU:STA
SDA
IN
TSP
TF
TLOW
THD:STA
THIGH
THD:DAT
TR
TSU:DAT
TSU:STO
SDA
OUT
TAA
THD:STA
TAA
TBUF
© 1996 Microchip Technology Inc.
DS21081D-page 3