24AA65 Datasheet, PDF (3/12 Pages) Microchip Technology – 64K 1.8V I 2 C O Smart Serial O EEPROM

24AA65
TABLE 1-3: AC CHARACTERISTICS
Parameter
Vcc = 1.8V - 6.0V Vcc = 4.5V - 6.0V
Symbol ^{STD. MODE}
FAST MODE _Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
—
100
—
400 kHz
Clock high time
THIGH 4000
—
600
—
ns
Clock low time
TLOW 4700
—
1300
—
ns
SDA and SCL rise time
TR
—
1000
—
300 ns (Note 1)
SDA and SCL fall time
TF
—
300
—
300 ns (Note 1)
START condition hold time
THD:STA 4000
—
600
—
ns After this period the
first clock pulse is gen-
erated
START condition setup time TSU:STA 4700
—
600
—
ns Only relevant for
repeated START condi-
tion
Data input hold time
THD:DAT
0
—
0
—
ns
Data input setup time
TSU:DAT 250
—
100
—
ns
STOP condition setup time
TSU:STO 4000
—
600
—
ns
Output valid from clock
TAA
—
3500
—
900 ns (Note 2)
Bus free time
TBUF 4700
—
1300
—
ns Time the bus must be
free before a new
transmission can start
Output fall time fro VIH min to
TOF
—
250 20 +0.1 250
ns (Note 1), CB ≤ 100 pF
VIL max
CB
Input filter spike suppression
TSP
—
50
(SDA and SCL pins)
—
50
ns (Note 3
Write cycle time
TWR
—
5
—
5
ms/ (Note 4)
page
Endurance
High Endurance Block
Rest of Array
10M
—
1M
—
10M
— cycles 25°C, Vcc = 5.0V, Block
1M
—
Mode (Note 5)
Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
THD:STA
THD:DAT
TSU:DAT _TSU:STO
SDA
IN
TSP
TAA
TAA
TBUF
SDA
OUT
© 1996 Microchip Technology Inc.
DS21056F-page 3