24AA515_08 Datasheet, PDF (3/24 Pages) Microchip Technology – 512K I2C™ CMOS Serial EEPROM

24AA515/24LC515/24FC515
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
1
FCLK Clock frequency
—
100
kHz 1.7V ≤ VCC ≤ 2.5V
—
400
2.5V ≤ VCC ≤ 5.5V
—
1000
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
2
THIGH Clock high time
4000
600
500
—
ns 1.7V ≤ VCC ≤ 2.5V
—
2.5V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
3
TLOW Clock low time
4700
1300
500
—
ns 1.7V ≤ VCC ≤ 2.5V
—
2.5V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
4
TR
SDA and SCL rise time
(Note 1)
—
1000
ns 1.7V ≤ VCC ≤ 2.5V
—
300
2.5V ≤ VCC ≤ 5.5V
—
300
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
5
TF
SDA and SCL fall time
(Note 1)
—
300
ns All except, 24FC515
—
100
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
6
THD:STA Start condition hold time
4000
600
250
—
ns 1.7V ≤ VCC ≤ 2.5V
—
2.5V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
7
TSU:STA Start condition setup time
4700
600
250
—
ns 1.7V ≤ VCC ≤ 2.5V
—
2.5V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
8
THD:DAT Data input hold time
0
—
ns (Note 2)
9
TSU:DAT Data input setup time
250
—
ns 1.7V ≤ VCC ≤ 2.5V
100
—
2.5V ≤ VCC ≤ 5.5V
100
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
10
TSU:STO Stop condition setup time
4000
600
250
—
ns 1.7V ≤ VCC ≤ 2.5V
—
2.5V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
11
TSU:WP WP setup time
4000
600
600
—
ns 1.7V ≤ VCC ≤ 2.5V
—
2.5V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
12
THD:WP WP hold time
4700
1300
1300
—
ns 1.7V ≤ VCC ≤ 2.5V
—
2.5V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
13
TAA
Output valid from clock
(Note 2)
—
3500
ns 1.7V ≤ VCC ≤ 2.5V
—
900
2.5V ≤ VCC ≤ 5.5V
—
400
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
14
TBUF Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
500
—
ns 1.7V ≤ VCC ≤ 2.5V
—
2.5V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
15
TOF
Output fall time from VIH
minimum to VIL maximum
CB ≤ 100 pF
10 + 0.1CB
250
250
ns All except, 24FC515 (Note 1)
24FC515 (Note 1)
16
TSP
Input filter spike suppression
—
(SDA and SCL pins)
50
ns All except, 24FC515 (Notes 1 and 3)
17
TWC
Write cycle time (byte or page)
—
5
ms
18
Endurance
1M
—
cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
© 2008 Microchip Technology Inc.
DS21673G-page 3