PIC16F1824 Datasheet, PDF (281/420 Pages) Microchip Technology – 14/20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16F/LF1824/1828
24.6.8 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSP1CON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP1 module then goes into Idle mode
(Figure 24-29).
24.6.8.1 WCOL Status Flag
If the user writes the SSP1BUF when an Acknowledge
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
24.6.9 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSP1CON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSP1STAT register is set. A TBRG later, the PEN bit is
cleared and the SSP1IF bit is set (Figure 24-30).
24.6.9.1 WCOL Status Flag
If the user writes the SSP1BUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 24-30: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSP1CON2
ACKEN = 1, ACKDT = 0
SDA
D0
TBRG
TBRG
ACK
ACKEN automatically cleared
SCL
8
9
SSP1IF
SSP1IF set at
the end of receive
Cleared in
software
Note: TBRG = one Baud Rate Generator period.
Cleared in
software
SSP1IF set at the end
of Acknowledge sequence
 2010 Microchip Technology Inc.
Preliminary
DS41419A-page 281