MCP2050 Datasheet, PDF (28/40 Pages) Microchip Technology – LIN Transceiver with Voltage Regulator

MCP2050
2.7 Timing Diagrams and Specifications
FIGURE 2-10:
BUS TIMING DIAGRAM
TXD
50%
50%
LBUS
RXD
tTRANSPDF
tRECPDF
50%
Internal TXD/RXD
Compare
Match
FAULT Sampling
Match
FAULT/TXE Output Stable
Hold
Value
Match
t_FAULT
Stable
.95VLBUS
.50VBB
.05VLBUS
tTRANSPDR
0.0V
tRECPDR
50%
Match
Match
Hold
Value
t_FAULT
Stable
FIGURE 2-11:
REGULATOR BUS WAKE TIMING DIAGRAM
LBUS
VREG-NOM
VREG
V_WK(LBUS)
t_BDB
t_BACTIVE
t_VEVR
DS20002299C-page 28
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