DSPIC33EPXXXGP50X Datasheet, PDF (265/504 Pages) Microchip Technology – 16-bit Microcontrollers and Digital Signal Controllers (up to 256 KB Flash and 32 KB SRAM) with High-Speed PWM, Op amps, and Advanced Analog

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
19.0 INTER-INTEGRATED
CIRCUIT™ (I²C™)
Note 1: This data sheet summarizes the features
of
the
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X,
and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 19. “Inter-Inte-
grated Circuit™ (I²C™)” (DS70330) of
the “dsPIC33E/PIC24E Family Refer-
ence Manual”, which is available from the
Microchip
web
site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X family of devices
contain two Inter-Integrated Circuit (I²C) modules: I2C1
and I2C2.
The I²C module provides complete hardware support
for both Slave and Multi-Master modes of the I²C serial
communication standard, with a 16-bit interface.
The I²C module has a 2-pin interface:
• The SCLx pin is clock.
• The SDAx pin is data.
The I²C module offers the following key features:
• I²C interface supporting both Master and Slave
modes of operation.
• I²C Slave mode supports 7 and 10-bit address.
• I²C Master mode supports 7 and 10-bit address.
• I²C port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for I²C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I²C supports multi-master operation, detects bus
collision and arbitrates accordingly.
• IPMI support
• SMBus support
© 2011 Microchip Technology Inc.
Preliminary
DS70657D-page 265