PIC16F84A-04-P Datasheet, PDF (26/90 Pages) Microchip Technology – 18-pin Enhanced FLASH/EEPROM 8-Bit Microcontroller

PIC16F84A
6.4 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for VDD
must be met for this to operate properly. See Electrical
Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
The POR circuit does not produce an internal RESET
when VDD declines.
6.5 Power-up Timer (PWRT)
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (TPWRT) from POR (Figures 6-6
through 6-9). The Power-up Timer operates on an
internal RC oscillator. The chip is kept in RESET as
long as the PWRT is active. The PWRT delay allows
the VDD to rise to an acceptable level (possible excep-
tion shown in Figure 6-9).
A configuration bit, PWRTE, can enable/disable the
PWRT. See Register 6-1 for the operation of the
PWRTE bit for a particular device.
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
6.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 6-6, Figure 6-7, Figure 6-8
and Figure 6-9). This ensures the crystal oscillator or
resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case
(Figure 6-9), an external Power-on Reset circuit may
be necessary (Figure 6-5).
FIGURE 6-5:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD VDD
D
R
C
R1
MCLR
PIC16FXX
Note
1: External Power-on Reset circuit is required
only if VDD power-up rate is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
degrade VIH level on the MCLR pin.
3: R1 = 100 to 1 k will limit any current flow-
ing into MCLR from external capacitor C, in
the event of a MCLR pin breakdown due to
ESD or EOS.
DS35007C-page 26
 2001-2013 Microchip Technology Inc.