PIC16F1783-I Datasheet, PDF (258/444 Pages) Microchip Technology – 28-Pin 8-Bit Advanced Analog Flash Microcontrollers

PIC16(L)F1782/3
25.2 Compare Mode
The Compare mode function described in this section
is available and identical for al CCP modules.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate an Auto-conversion Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
Figure 25-2 shows a simplified diagram of the compare
operation.
FIGURE 25-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCPxM<3:0>
Mode Select
CCPx
Pin
Set CCPxIF Interrupt Flag
4 ^(PIRx)
CCPRxH CCPRxL
Q S _Output
R ^Logic
Match
Comparator
TRIS
Output Enable
TMR1H TMR1L
Auto-conversion Trigger
25.2.1 CCPX PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
The CCP2 pin function can be moved to alternate pins
using the APFCON register (Register 13-1). Refer to
Section 13.1 “Alternate Pin Function” for more
details.
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
25.2.2 TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 22.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
25.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
25.2.4 AUTO-CONVERSION TRIGGER
When Auto-conversion Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
pin in this mode.
The Auto-conversion Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL regis-
ter pair. The TMR1H, TMR1L register pair is not reset
until the next rising edge of the Timer1 clock. The
Auto-conversion Trigger output starts an A/D conver-
sion (if the A/D module is enabled). This allows the
CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1.
Refer to Section 17.2.5 “Auto-Conversion Trigger”
for more information.
Note 1: The Auto-conversion Trigger from the
CCP module does not set interrupt flag
bit TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the
Auto-conversion Trigger and the clock
edge that generates the Timer1 Reset,
will preclude the Reset from occurring.
DS41579C-page 258
Preliminary
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