PIC16F1516-I Datasheet, PDF (258/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1516/7/8/9
FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 22-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
INTCON
GIE
PEIE TMR0IE INTE
IOCIE TMR0IF INTF
IOCIF
PIE1
TMR1GIE ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
RCREG
EUSART Receive Data Register
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
SPBRGL
BRG<7:0>
SPBRGH
BRG<15:8>
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
245
76
77
79
238*
244
246*
246*
117
243
DS41452C-page 258
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