MCP65R41 Datasheet, PDF (23/34 Pages) Microchip Technology – 3 uA Comparator with Integrated Reference Voltage

4.3.2 INVERTING CIRCUIT
Figure 4-6 shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
V_IN
V_REF
V_DD
V_PU
R_PU*
V_OUT
R₂
R₃
R_F
* Pull-up resistor required for the MCP65R46 only.
FIGURE 4-6:
Hysteresis.
Inverting Circuit with
V_DD
V_OH
V_OUT
Low-to-High
High-to-Low
V_OL
V_SS
V_SS
V_TLH V_THL
V_IN
V_DD
FIGURE 4-7:
Hysteresis Diagram for the
Inverting Circuit.
In order to determine the trip voltages (V_THL and V_TLH)
for the circuit shown in Figure 4-6, R₂ and R₃ can be
simplified to the Thevenin equivalent circuit with
respect to V_REF, as shown in Figure 4-8:
V_DD
V_PU
-
R_PU*
+
V_SS
V_OUT
V₂₃
R₂₃
R_F
Where:
R₂₃
=
----R----²---R---³----
R₂ + R₃
V₂₃
=
-------R----³-------
R₂ + R₃

V_REF
* Pull-up resistor required for the MCP65R46 only.
FIGURE 4-8:
Thevenin Equivalent Circuit.
 2010 Microchip Technology Inc.
MCP65R41/6
By using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-1:
V_THL
=

V_{O H }
R----₂^---₃^{-R---+-2--3--R----F--}_{}
+ V_{23R----2}---₃-R---+-^F----R----_F-_
V_TLH
=
V_O
L



R----₂^---₃^{-R---+-2--3--R----F--}_{}
+
V₂₃


-R---₂---₃-R---+-^F----R----_F-_
Where:
V_TLH = trip voltage from low to high
V_THL = trip voltage from high to low
Figures 2-23 and 2-26 can be used to determine the
typical values for V_OH and V_OL.
4.4 Bypass Capacitors
With this family of comparators, the power supply pin
(V_DD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
4.5 Capacitive Loads
4.5.1 OUT PIN
Reasonable capacitive loads (e.g., logic gates) have
little impact on the propagation delay (see Figure 2-34).
The supply current increases with the increasing toggle
frequency (Figure 2-22), especially with higher
capacitive loads. The output slew rate and propagation
delay performance will be reduced with higher capaci-
tive loads.
4.5.2
V_REF PIN
The reference output is designed to interface to the
comparator input pins, either directly or with some
resistive network, such as voltage divider network, with
minimal capacitive load. The recommended capacitive
load is 200 pF (typical). Capacitive loads greater than
2000 pF may cause the V_REF output to oscillate at
power up.
DS22269A-page 23