DSPIC30F6010A_11 Datasheet, PDF (229/236 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F6010A/6015
Register Map (dsPIC30F6015) .................................. 47
Interrupt Priority ................................................................. 42
Interrupt Sequence ............................................................ 45
Interrupt Stack Frame ................................................ 45
Interrupts ............................................................................ 41
I²C Master Operation
Baud Rate Generator ............................................... 116
Clock Arbitration ....................................................... 117
Multi-Master Communication, Bus Collision and Bus Ar-
bitration ............................................................ 117
Reception ................................................................. 116
Transmission ............................................................ 116
I²C Module
Addresses ................................................................ 114
General Call Address Support ................................. 116
Interrupts .................................................................. 116
IPMI Support ............................................................ 116
Master Operation ..................................................... 116
Master Support ........................................................ 116
Operating Function Description ............................... 112
Operation During CPU Sleep and Idle Modes ......... 117
Pin Configuration ..................................................... 112
Programmer’s Model ................................................ 112
Register Map ............................................................ 118
Registers .................................................................. 112
Slope Control ........................................................... 116
Software Controlled Clock Stretching (STREN = 1) . 115
Various Modes ......................................................... 112
I²C 10-bit Slave Mode Operation ..................................... 114
10-bit Mode Slave Reception ................................... 115
10-bit Mode Slave Transmission .............................. 115
I²C 7-bit Slave Mode Operation ....................................... 114
Reception ................................................................. 114
Transmission ............................................................ 114
I²C™ Module ................................................................... 112
M
Memory Organization ......................................................... 23
Core Register Map ..................................................... 32
Microchip Internet Web Site ............................................. 231
Modulo Addressing ............................................................ 36
Applicability ................................................................ 38
Operation Example .................................................... 37
Start and End Address ............................................... 37
W Address Register Selection ................................... 37
Motor Control PWM Module ............................................... 97
8-Output Register Map ............................................. 107
MPLAB ASM30 Assembler, Linker, Librarian .................. 176
MPLAB Integrated Development Environment Software . 175
MPLAB PM3 Device Programmer ................................... 178
MPLAB REAL ICE In-Circuit Emulator System ................ 177
MPLINK Object Linker/MPLIB Object Librarian ............... 176
O
Operating Current (IDD) .................................................... 182
Oscillator
Operating Modes (Table) ......................................... 153
System Overview ..................................................... 152
Oscillator Configurations .................................................. 155
Fail-Safe Clock Monitor ............................................ 157
Fast RC (FRC) ......................................................... 156
Initial Clock Source Selection .................................. 155
Low-Power RC (LPRC) ............................................ 157
LP Oscillator Control ................................................ 156
Phase Locked Loop (PLL) ....................................... 156
Start-up Timer (OST) ............................................... 156
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Oscillator Selection .......................................................... 152
Output Compare Module ................................................... 85
Interrupts ................................................................... 88
Operation During CPU Idle Mode .............................. 88
Operation During CPU Sleep Mode .......................... 88
Register Map ............................................................. 89
P
Packaging Information ..................................................... 219
Marking .................................................................... 219
Peripheral Module Disable (PMD) Registers ................... 164
Pin Diagrams ................................................................... 5–6
Pinout Descriptions ............................................................ 12
POR. See Power-on Reset.
Position Measurement Mode ............................................. 92
Power Saving Modes
Idle ........................................................................... 163
Sleep ....................................................................... 162
Power-on Reset (POR) .................................................... 152
Oscillator Start-up Timer (OST) ............................... 152
Power-up Timer (PWRT) ......................................... 152
Power-Saving Modes ....................................................... 162
Power-Saving Modes (Sleep and Idle) ............................ 152
Program Address Space .................................................... 23
Construction .............................................................. 24
Data Access from Program Memory Using
Table Instructions .............................................. 25
Data Access from, Address Generation .................... 24
Memory Map .............................................................. 23
Table Instructions
TBLRDH ............................................................ 25
TBLRDL ............................................................. 25
TBLWTH ............................................................ 25
TBLWTL ............................................................ 25
Program Counter ............................................................... 16
Program Data Table Access .............................................. 26
Program Space Visibility
Window into Program Space Operation .................... 27
Programmable ................................................................. 152
Programmable Digital Noise Filters ................................... 93
Programmer’s Model ......................................................... 16
Diagram ..................................................................... 17
Programming Operations ................................................... 51
Algorithm for Program Flash ...................................... 51
Erasing a Row of Program Memory .......................... 51
Initiating the Programming Sequence ....................... 52
Loading Write Latches ............................................... 52
Protection Against Accidental Writes to OSCCON .......... 158
PWM Duty Cycle Comparison Units ................................ 101
Duty Cycle Immediate Updates ............................... 102
Duty Cycle Register Buffers .................................... 102
PWM Fault Pins ............................................................... 105
Enable Bits .............................................................. 105
Fault States ............................................................. 105
Input Modes ............................................................. 105
Cycle-by-Cycle ................................................ 105
Latched ............................................................ 105
Priority ..................................................................... 105
PWM Operation During CPU Idle Mode .......................... 106
PWM Operation During CPU Sleep Mode ....................... 106
PWM Output and Polarity Control .................................... 105
Output Pin Control ................................................... 105
PWM Output Override ..................................................... 104
Complementary Output Mode ................................. 104
Synchronization ....................................................... 104
PWM Period ..................................................................... 100
DS70150E-page 229