MCP3004_08 Datasheet, PDF (22/40 Pages) Microchip Technology – 2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface

MCP3004/3008
CS
SCLK
D_IN
MCU latches data from A/D converter
on rising edges of SCLK
1234567
8 9 10 11 12 13 14 15
Data is clocked out of A/D
converter on falling edges
Start
SGL/
DIFF
D2
D1
DO
16 17 18 19 20 21 22 23 24
Don’t Care
D_OUT
HI-Z
MCU Transmitted Data
Start
Bit
(Aligned with falling
edge of clock)
000 0000 1
MCU Received Data
(Aligned with rising
edge of clock)
????????
X = “Don’t Care” Bits
Data stored into MCU receive
register after transmission of first
8 bits
NULL
BIT ^{B9 B8 B7 B6 B5 B4 B3 B2 B1 B0}
SGL/
DIFF
D2
D1 DO
X
X
X
X
?
?
?
?
?
0
(Null)
B9
B8
Data stored into MCU receive
register after transmission of
second 8 bits
XXXXX XXX
B7 B6 B5 B4 B3 B2 B1 B0
Data stored into MCU receive
register after transmission of last
8 bits
FIGURE 6-2:
SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 1,1: SCLK idles high).
6.2 Maintaining Minimum Clock Speed
When the MCP3004/3008 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample capacitor while the conversion is
taking place. At 85°C (worst case condition), the part
will maintain proper charge on the sample capacitor for
at least 1.2 ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 10 data bits have been
clocked out must not exceed 1.2 ms (effective clock
frequency of 10 kHz). Failure to meet this criterion may
introduce linearity errors into the conversion outside
the rated specifications. It should be noted that during
the entire conversion cycle, the A/D converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
6.3 Buffering/Filtering the Analog
Inputs
If the signal source for the A/D converter is not a low-
impedance source, it will have to be buffered or
inaccurate conversion results may occur (see Figure 4-
2). It is also recommended that a filter be used to
eliminate any signals that may be aliased back in to the
conversion results, as is illustrated in Figure 6-3, where
an op amp is used to drive, filter and gain the analog
input of the MCP3004/3008. This amplifier provides a
low-impedance source for the converter input, plus a
low-pass filter, which eliminates unwanted high-
frequency noise.
Low-pass (anti-aliasing) filters can be designed using
Microchip’s free interactive FilterLab^® software.
FilterLab will calculate capacitor and resistors values,
as well as determine the number of poles that are
required for the application. For more information on fil-
tering signals, see AN699, “Anti-Aliasing Analog Filters
for Data Acquisition Systems”.
4.096V
Reference
0.1 µF
1 µF
MCP1541
V_DD
10 µF
1 µF
R₁ ^C1
V_IN
R₂
C₂
MCP601
+
-
R₃^R4
IN+ _VREF
MCP3004
IN-
FIGURE 6-3:
The MCP601 Operational
Amplifier is used to implement a second order
anti-aliasing filter for the signal being converted
by the MCP3004.
DS21295D-page 22
© 2008 Microchip Technology Inc.