TC1313_09 Datasheet, PDF (21/32 Pages) Microchip Technology – 500 mA Synchronous Buck Regulator, + 300 mA LDO

For example, for a 3.6V input, 1.8V output with a load
of 400 mA, the efficiency taken from Figure 2-7 is
approximately 84%. The internal power dissipation is
approximately 137 mW.
5.6.2
LDO OUTPUT (V_OUT2)
The internal power dissipation within the TC1313 LDO
is a function of input voltage, output voltage and output
current. The following equation can be used to
calculate the internal power dissipation for the LDO.
EQUATION 5-7:
P_LDO = (V_IN(MAX) – V_OUT2(MIN)) × I_OUT2(MAX)
Where:
P_LDO = LDO Pass device internal power
dissipation
V_IN(MAX) = Maximum input voltage
V_OUT(MIN) = LDO minimum output voltage
The maximum power dissipation capability for a
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient
temperature for the application. The following equation
can be used to determine the package’s maximum
internal power dissipation.
5.6.3
LDO POWER DISSIPATION
EXAMPLE
Input Voltage
V_IN = 5V ±10%
LDO Output Voltage and Current
V_OUT = 3.3V
I_OUT = 300 mA
Internal Power Dissipation
P_LDO(MAX) = (V_IN(MAX) – V_OUT2(MIN)) x I_OUT2(MAX)
P_LDO = (5.5V) – (0.975 x 3.3V))
x 300 mA
P_LDO = 684.8 mW
5.7 PCB Layout Information
Some basic design guidelines should be used when
physically placing the TC1313 on a Printed Circuit
Board (PCB). The TC1313 has two ground pins,
identified as A_GND (analog ground) and P_GND (power
ground). By separating grounds, it is possible to
minimize the switching frequency noise on the LDO
output. The first priority, while placing external
components on the board, is the input capacitor (C_IN1).
Wiring should be short and wide; the input current for
the TC1313 can be as high as 800 mA. The next
priority would be the buck regulator output capacitor
(C_OUT1) and inductor (L₁). All three of these
components are placed near their respective pins to
© 2009 Microchip Technology Inc.
TC1313
minimize trace length. The C_IN1 and C_OUT1 capacitor
returns are connected closely together at the P_GND
plane. The LDO optional input capacitor (C_IN2) and
LDO output capacitor C_OUT2 are returned to the A_GND
plane. The analog ground plane and power ground
plane are connected at one point (shown near L₁). All
other signals (SHDN1, SHDN2, feedback in the
adjustable output case) should be referenced to A_GND
and have the A_GND plane underneath them.
- Via
A_GND to P_GND
* C_IN2 Optional
A_GND
C_{IN2 1}
+V_IN2
2
+V_OUT2
3
C_OUT2
4
5
A_GND
+V_OUT1
L₁
C_OUT1
10
9
8
7
TC1313 ⁶
P_GND
C_IN1
+V_IN1
P_GND Plane
A_GND Plane
FIGURE 5-1:
Component Placement,
Fixed-Output 10-Pin MSOP.
There will be some difference in layout for the 10-pin
DFN package due to the thermal pad. A typical fixed-
output DFN layout is shown below. For the DFN layout,
the V_IN1 to V_IN2 connection is routed on the bottom of
the board around the TC1313 thermal pad.
- Via
A_GND to P_GND
* C_IN2 Optional
A_GND
PGND
C_OUT1
+V_OUT1
L₁
C_IN2
1
+V_IN2
2
+V_OUT2
3
4
C_OUT2
5
A_GND
10
P_GND
9
C_IN1
8
7
+V_IN1
6
TC1313
P_GND Plane
A_GND Plane
FIGURE 5-2:
Component Placement,
Fixed-Output 10-Pin DFN.
DS21974B-page 21