DSPIC30F1010-20E Datasheet, PDF (207/286 Pages) Microchip Technology – dsPIC30F1010/202X Data Sheet

dsPIC30F1010/202X
18.2.1 ACCIDENTAL WRITE PROTECTION
Because the OSCCON register allows clock switching
and clock scaling, a write to OSCCON is intentionally
made difficult. To write to the OSCCON low byte, this
exact sequence must be executed without any other
instructions in between:
• Byte Write “46h” to OSCCON low
• Byte Write “57h” to OSCCON low
• Byte Write is allowed for one instruction cycle
mov.b W0,OSCCON
To write to the OSCCON high byte, this exact
sequence must be executed without any other instruc-
tions in between:
• Byte Write “78h” to OSCCON high
• Byte Write “9Ah” to OSCCON high
• Byte Write is allowed for one instruction cycle
mov.b W0,OSCCON + 1
18.3 Oscillator Configurations
Figure 18-2 shows the derivation of the system clock
FCY. The PLL in Figure 18-1 outputs a maximum fre-
quency of 480MHz (high-range FRC option for
industrial temperature parts with PLL and TUN<3:0> =
0111 bit settings). This signal is used by the Power
Supply PWM module, and is 32 times the input PLL fre-
quency.
Assuming the high-range FRC option is selected on an
industrial temperature rated part, the 480 MHz PLL
clock signal is divided by 2, providing a 240 MHz signal,
which drives the ADC Module. The same 480 MHz sig-
nal is also divided by 8 to produce the 60 MHz signal,
which is one of the inputs to the FCY multiplexer. The
other input to this multiplexer is the FOSC input clock
source (either the Primary Oscillator or the FRC)
divided by 2. When the PLL is enabled, FCY = FPLL/16.
When the PLL is disabled, FCY = FOSC/2.
This method derives the 480 MHz clock:
• FRC Clock with high-range Option and TUN<3:0>
= 0111 is = 15 MHz
• PLL enabled
• PWM clock = 15 x 32 = 480 MHz
• FCY = 480 MHz/16 = 30 MHz = 30 MIPS
If the PLL is disabled,
• FRC Clock (with high-range Option and
TUN<3:0> = 0111) is = 15MHz
• FCY = 15 MHz/2 = 7.5 MHz = 7.5 MIPS
FIGURE 18-2:
SYSTEM CLOCK AND FADC DERIVATION
PLL Enable
PLL – 192-480 MHZ
FPLL
Primary Oscillator
FRC
Divide
By 2
96-240 MHZ
1
FADC
0
Divide
24-60 MHZ
By 8
1
Divide
By 2
FCY
0
FOSC
PLL Enable
Oscillator Configuration Bits
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 205