MIC4102 Datasheet, PDF (20/28 Pages) Micrel Semiconductor – 100V Half Bridge MOSFET Driver with Anti-Shoot Through Protection

MIC4102
C_VDD
V_DD
CHARGE C_B THROUGH
INTERNAL DIODE WHEN
HS PIN IS LOW
HB
V
V
HO
C_B
HS
HIGH-SIDE DRIVE
TURN-OFF CURRENT PATH
LOW-SIDE DRIVE TURN-OFF
CURRENT PATH
LO
V
LEVEL
SHIFT
V_SS
_
Q
FF
Q
PWM
LS
FIGURE 6-6:
Turn-Off Current Paths.
The following circuit guidelines should be adhered to
for optimum circuit performance:
• The V_DD and HB bypass capacitors must be
placed close to the supply and ground pins. It is
critical that the etch length between the high side
decoupling capacitor (C_B) and the HB and HS
pins be minimized to reduce lead inductance.
• A ground plane should be used to minimize
parasitic inductance and impedance of the return
paths. The MIC4102 is capable of greater than 3A
peak currents. Any impedance between the
MIC4102, the decoupling capacitors, and the
external MOSFET will degrade the performance
of the driver.
• Trace out the high d_i/d_t and d_v/d_t paths, as shown
in Figure 6-5 and Figure 6-6 to minimize the etch
length and loop area for these connections.
Minimizing these parameters decreases the
parasitic inductance and the radiated EMI
generated by fast rise and fall times.
A typical layout of a synchronous buck converter power
stage using the MIC4102 (Figure 6-7) is shown in
Figure 6-8.
C_VDD
V_DD
V_DD
LEVEL
SHIFT
PWM
Q
FF_
Q
C_B
HB
HO
HS
LO
V_IN
HIGH-SIDE
FET
HS
(SWITCH NODE)
LOW-SIDE
C_IN
FET
V_SS
FIGURE 6-7:
Stage.
Typical Converter Power
FIGURE 6-8:
Typical Layout of a
Synchronous Buck Converter Power Stage.
The circuit is configured as a synchronous buck power
stage. The high-side MOSFET drain connects to the
input supply voltage (drain) and the source connects to
the switching node. The low-side MOSFET drain
connects to the switching node and its source is
connected to ground. The buck converter output
inductor (not shown) would connect to the switching
node. The high-side drive trace, HO, is routed on top
of its return trace, HS, to minimize loop area and
parasitic inductance. The low-side drive trace, LO, is
routed over the ground plane and minimizes the
impedance of that current path. The decoupling
capacitors, C_B and C_VDD, are placed to minimize etch
length between the capacitors and their respective
pins. This close placement is necessary to efficiently
charge capacitor C_B when the HS node is low. All
traces are 0.025” wide or greater to reduce impedance.
C_IN is used to decouple the high current path through
the MOSFETs.
DS20005575A-page 20
 2016 Microchip Technology Inc.