41594B Datasheet, PDF (20/372 Pages) Microchip Technology – 8-Bit Flash Microcontroller with nanoWatt XLP Technology

TABLE 3-3: PIC12LF1840T48A MEMORY MAP, BANKS 0-7
BANK 0
BANK 1
BANK 2
BANK 3
000h
INDF0
080h
INDF0
100h
INDF0
180h
INDF0
001h
INDF1
081h
INDF1
101h
INDF1
181h
INDF1
002h
PCL
082h
PCL
102h
PCL
182h
PCL
003h
STATUS
083h
STATUS
103h
STATUS
183h
STATUS
004h
FSR0L
084h
FSR0L
104h
FSR0L
184h
FSR0L
005h
FSR0H
085h
FSR0H
105h
FSR0H
185h
FSR0H
006h
FSR1L
086h
FSR1L
106h
FSR1L
186h
FSR1L
007h
FSR1H
087h
FSR1H
107h
FSR1H
187h
FSR1H
008h
BSR
088h
BSR
108h
BSR
188h
BSR
009h
WREG
089h
WREG
109h
WREG
189h
WREG
00Ah
PCLATH
08Ah
PCLATH
10Ah
PCLATH
18Ah
PCLATH
00Bh
INTCON
08Bh
INTCON
10Bh
INTCON
18Bh
INTCON
00Ch
PORTA
08Ch
TRISA
10Ch
LATA
18Ch
ANSELA
00Dh
—
08Dh
—
10Dh
—
18Dh
—
00Eh
—
08Eh
—
10Eh
—
18Eh
—
00Fh
—
08Fh
—
10Fh
—
18Fh
—
010h
—
090h
—
110h
—
190h
—
011h
PIR1
091h
PIE1
111h CM1CON0 191h
EEADRL
012h
PIR2
092h
PIE2
112h CM1CON1 192h
EEADRH
013h
—
093h
—
113h
—
193h
EEDATL
014h
—
094h
—
114h
—
194h
EEDATH
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
EECON1
EECON2
—
—
RCREG
TXREG
SPBRGL
SPBRGH
01Dh
01Eh
—
CPSCON0
09Dh
09Eh
ADCON0
ADCON1
11Dh
11Eh
APFCON
—
19Dh
19Eh
RCSTA
TXSTA
01Fh CPSCON1 09Fh
—
11Fh
—
19Fh BAUDCON
020h
0A0h
120h
1A0h
06Fh
070h
General
Purpose
Register
96 Bytes
0BFh
0EFh
0F0h
General
Purpose
Register
80 Bytes
16Fh
170h
General
Purpose
Register
80 Bytes
Unimplemented
Read as ‘0’
1EFh
1F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
07Fh
0FFh
17Fh
1FFh
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
26Fh
270h
27Fh
BANK 4
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUA
—
—
—
—
SSPBUF
SSPADD
SSPMASK
SSPSTAT
SSPCON
SSPCON2
SSPCON3
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
BANK 5
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
36Fh
370h
37Fh
BANK 6
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
BANK 7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
IOCAP
IOCAN
IOCAF
—
—
—
—
—
—
CLKRCON
—
MDCON
MDSRC
MDCARL
MDCARH
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.