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PIC24FJ256GB106-IMR Datasheet, PDF (199/352 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) | |||
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PIC24FJ256GB110 FAMILY
17.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
âPIC24F Family Reference Manualâ,
Section 21. âUARTâ (DS39708).
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the PIC24F device family. The UART is a full-duplex
asynchronous system that can communicate with
peripheral devices, such as personal computers, LIN,
RS-232 and RS-485 interfaces. The module also sup-
ports a hardware flow control option with the UxCTS and
UxRTS pins and also includes an IrDA® encoder and
decoder.
The primary features of the UART module are:
⢠Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
⢠Even, Odd or No Parity Options (for 8-bit data)
⢠One or two Stop bits
⢠Hardware Flow Control Option with UxCTS and
UxRTS Pins
⢠Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
⢠Baud Rates Ranging from 1 Mbps to 15 bps at
16 MIPS
⢠4-Deep, First-In-First-Out (FIFO) Transmit Data
Buffer
⢠4-Deep FIFO Receive Data Buffer
⢠Parity, Framing and Buffer Overrun Error Detection
⢠Support for 9-bit mode with Address Detect
(9th bit = 1)
⢠Transmit and Receive Interrupts
⢠Loopback mode for Diagnostic Support
⢠Support for Sync and Break Characters
⢠Supports Automatic Baud Rate Detection
⢠IrDA Encoder and Decoder Logic
⢠16x Baud Clock Output for IrDA® Support
A simplified block diagram of the UART is shown in
Figure 17-1. The UART module consists of these key
important hardware elements:
⢠Baud Rate Generator
⢠Asynchronous Transmitter
⢠Asynchronous Receiver
FIGURE 17-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
UARTx Receiver
UxRTS/BCLKx
UxCTS
UxRX
UARTx Transmitter
UxTX
Note: The UART inputs and outputs must all be assigned to available RPn pins before use. Please see
Section 10.4 âPeripheral Pin Selectâ for more information.
ï£ 2009 Microchip Technology Inc.
DS39897C-page 199
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