DSPIC33FJ128MC706-I Datasheet, PDF (196/340 Pages) Microchip Technology – 16-Bit Digital Signal Controllers

dsPIC33FJXXXMCX06/X08/X10
REGISTER 17-2: DFLTxCON: DIGITAL FILTER CONTROL REGISTER
U-0
—
bit 15
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
IMV<1:0>
R/W-0
CEID
bit 8
R/W-0
QEOUT
bit 7
R/W-0
QECK<2:0>
U-0
U-0
U-0
U-0
—
—
—
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
bit 10-9
bit 8
bit 7
bit 6-4
bit 3-0
Unimplemented: Read as ‘0’
IMV<1:0>: Index Match Value bits – These bits allow the user to specify the state of the QEAx and
QEBx input pins during an index pulse when the POSxCNT register is to be reset
In 4X Quadrature Count Mode:
IMV1 = Required state of Phase B input signal for match on index pulse
IMV0 = Required state of Phase A input signal for match on index pulse
In 2X Quadrature Count Mode:
IMV1 = Selects phase input signal for index state match (0 = Phase A, 1 = Phase B)
IMV0 = Required state of the selected Phase input signal for match on index pulse
CEID: Count Error Interrupt Disable bit
1 = Interrupts due to count errors are disabled
0 = Interrupts due to count errors are enabled
QEOUT: QEAx/QEBx/INDXx Pin Digital Filter Output Enable bit
1 = Digital filter outputs enabled
0 = Digital filter outputs disabled (normal pin operation)
QECK<2:0>: QEAx/QEBx/INDXx Digital Filter Clock Divide Select Bits
111 = 1:256 Clock Divide
110 = 1:128 Clock Divide
101 = 1:64 Clock Divide
100 = 1:32 Clock Divide
011 = 1:16 Clock Divide
010 = 1:4 Clock Divide
001 = 1:2 Clock Divide
000 = 1:1 Clock Divide
Unimplemented: Read as ‘0’
DS70287C-page 194
© 2009 Microchip Technology Inc.