SST26WF016B Datasheet, PDF (19/75 Pages) Microchip Technology – 1.8V 16 Mbit Serial Quad I/O (SQI) Flash Memory

SST26WF016B/SST26WF016BA
5.8 SPI Quad I/O Read
The SPI Quad I/O Read (SQIOR) instruction supports
up to 104 MHz frequency. SST26WF016B requires the
IOC bit in the configuration register to be set to ‘1’ prior
to executing the command. Initiate SQIOR by execut-
ing an 8-bit command, EBH. The device then switches
to 4-bit I/O mode for address bits A[23-0], followed by
the Set Mode configuration bits M[7:0], and two dummy
bytes.CE# must remain active low for the duration of
the SPI Quad I/O Read. See Figure 5-9 for the SPI
Quad I/O Read sequence.
Following the dummy bytes, the device outputs data
from the specified address location. The device contin-
ually streams data output through all addresses until
terminated by a low-to-high transition on CE#. The
internal address pointer automatically increments until
the highest memory address is reached, at which point
the address pointer returns to the beginning of the
address space.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Quad I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another Read com-
mand, EBH, and does not require the op-code to be
entered again. The host may set the next SQIOR cycle
by driving CE# low, then sending the four-bit wide input
for address A[23:0], followed by the Set Mode configu-
ration bits M[7:0], and two dummy cycles. After the two
dummy cycles, the device outputs the data starting
from the specified address location. There are no
restrictions on address location access.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command, FFH. See Fig-
ure 5-10 for the SPI Quad I/O Mode Read sequence
when M[7:0] = AXH.
FIGURE 5-9:
SPI QUAD I/O READ SEQUENCE
CE#
SCK
MODE 3 _{0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23}
MODE 0
SIO0
EBH
A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 b4 b0
SIO1
A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 b5 b1
SIO2
SIO3
A22 A18 A14 A10 A6 A2 M6 M2 X X X X b6 b2 b6 b2
MSN LSN
A23 A19 A15 A11 A7 A3 M7 M3 X X X X b7 b3 b7 b3
Address
Set
Data Data
Mode ^Dummy Byte 0 Byte 1
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
1432 F49.2
 2014 Microchip Technology Inc.
DS20005013D-page 19