DSPIC30F1010X Datasheet, PDF (181/274 Pages) Microchip Technology – 28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers

16.14 ADC Base Register
It is expected that the user application may have the
ADC module generate 500,000 interrupts per second.
To speed the evaluation of the PxRDY bits in the
ADSTAT register, the ADC module features the read/
write register: ADBASE. When read, the ADBASE reg-
ister will provide a sum of the contents of the ADBASE
register plus an encoding of the PxRDY bits set in the
ADSTAT register.
The Least Significant bit of the ADBASE register is
forced to zero. This ensures that all (ADBASE +
PxRDY) results will be on instruction boundaries.
The PxRDY bits are binary priority encoded with
P0RDY being the highest priority, and P5RDY being
the lowest priority. The encoded priority result is then
shifted left two bit positions and added to the contents
of the ADBASE register. This means the priority
encoding yields addresses that are on two instruction
word boundaries.
The user will typically load the ADBASE register with
the base address of a “Jump” table that contains either
the addresses of the appropriate ISRs or branches to
the appropriate ISR. The encoded PxRDY values are
set up to reserve two instruction words per entry in the
Jump table. It is expected that the user software will
use one instruction word to load an identifier into a W
register, and the other instruction will be a branch to
the appropriate ISR.
16.15 Changing A/D Clock
In general, the A/D cannot accept changes to the ADC
clock divisor while ADON = 1. If the user makes A/D
clock changes while ADON = 1, the results will be
indeterminate.
dsPIC30F1010/202X
16.16 Sample and Conversion
The ADC module always assigns two ADC clock peri-
ods for the sampling process. When operating at the
maximum conversion rate of 2 Msps per channel, the
sampling period is:
2 x 41.6 nsec = 83.3 nsec.
Each ADC pair specified in the CPCx registers initiates
a sample operation when the selected trigger event
occurs. The conversion of the sampled analog data
occurs as resources become available.
If a new trigger event occurs for a specific channel
before a previous sample and convert request for that
channel has been processed, the newer request is
ignored. It is the user’s responsibility not to exceed the
conversion rate capability for the module.
The actual conversion process requires 10 additional
ADC clocks. The conversion is processed serially, bit 9
first, then bit 8, down to bit 0. The result is stored when
the conversion is completed.
16.17 A/D Sample and Convert Timing
The sample and hold circuits assigned to the input
pins have their own timing logic that is triggered when
an external sample and convert request (from PWM or
TMR) is made. The sample and hold circuits have a
fixed two clock data sample period. When the sample
has been acquired, then the ADC control logic is
notified of a pending request, then the conversion is
performed as the conversion resources become
available.
The ADC module always converts pairs of analog
input channels, so a typical conversion process
requires 24 clock cycles.
© 2006 Microchip Technology Inc.
Advance Information
DS70178A-page 179