TC850 Datasheet, PDF (18/26 Pages) TelCom Semiconductor, Inc – 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER

TC850
Internal Clock
CS ^. CE
WR
BUSY
....
........
1100 Clock Cycles
WR Pulses are Ignored
319 Clock
Cycles
836 Clock Cycles
Next Convert
Command will be
Recognized
125 Clock
Cycles
Next Conversion
can Begin
DB0-DB7
Previous Conversion
Data Valid
Data Meaningless
FIGURE 8-4:
Conversion Timing, Demand Mode
CS ^. CE
RD
TCE
TRE
*
New Conversion Data Valid
TDHC
TDHR
DB0-DB6
HI-Z
Data Bits 8 to 14
Data Bits 0 tp 6
High-Impedance
DB7
HI-Z
OVR/POL
L/H
"1"= Input
Overrange
tOP
"1"= Positive
Polarity
TLH
Data Bit 7
High-Impedance
Don't Care
Don't Care
NOTE: CONT/DEMAND = LOW
*RD (as well as CS and CE) can go HIGH after each byte is read (i.e., in a mP bus interface)
or remain LOW during the entire DATA-READ sequence (i.e., mP I/O port interface).
FIGURE 8-5:
Bus Output Timing, Demand Mode
DS21479C-page 18
© 2006 Microchip Technology Inc.