MIC28511 Datasheet, PDF (17/34 Pages) Microchip Technology – 60VIN, 3A Synchronous Buck Regulator

MIC28511
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Pin Number Symbol
Description
1
2
3
4, 7, 8, 9, 25
(25 is ePad)
5
6
10, 11, 22, 23,
26
(26 is ePad)
12, 21, 27
(27 is ePad)
13
14
15
16
17
18
19
20
24
DL
PGND
DH
PV_IN
LX
BST
PGND
SW
AGND
FB
PGOOD
EN
V_IN
I_LIM
V_DD
P_VDD
FREQ
Low-Side Gate Drive. Internal low-side power MOSFET gate connection. This pin must
be left unconnected or floating.
PGND is the return path for the low-side driver circuit. Connect to the source of low-side
MOSFET’s (PGND, pins 10, 11 22, 23, and 26) through a low-impedance path.
High-Side Gate Drive. Internal high-side power MOSFET gate connection. This pin
must be left unconnected or floating.
Power Input Voltage. The PV_IN pins supply power to the internal power switch. Connect
all PV_IN pins together and bypass locally with ceramic capacitors. The positive terminal
of the input capacitor should be placed as close as possible to the PV_IN pins, the
negative terminal of the input capacitor should be placed as close as possible to the
PGND pins 10,11, 22, 23, and 26.
The LX pin is the return path for the high-side driver circuit. Connect the negative
terminal of the bootstrap capacitor directly to this pin. Also connect this pin to the SW
pins 12, 21, and 27, with a low-impedance path. The controller monitors voltages on this
and PGND for zero current detection.
Bootstrap Pin. This pin provides bootstrap supply for the high-side gate driver circuit.
Connect a 0.1 µF capacitor and an optional resistor in series from the LX (pin 5) to the
BST.
Power Ground. These pins are connected to the source of the low-side MOSFET. They
are the return path for the step-down regulator power stage and should be tied together.
The negative terminal of the input decoupling capacitor should be placed as close as
possible to these pins.
Switch Node. The SW pins are the internal power switch outputs. These pins should be
tied together and connected to the output inductor.
Analog Ground. The analog ground for V_DD and the control circuitry. The analog ground
return path should be separate from the power ground (PGND) return path.
Feedback Input. The FB pin sets the regulated output voltage relative to the internal
reference. This pin is connected to a resistor divider from the regulated output such that
the FB pin is at 0.8V when the output is at the desired voltage.
The power good output is an open drain output requiring an external pull-up resistor to
external bias. This pin is a high impedance open circuit when the voltage at FB pin is
higher than 90% of the feedback reference voltage (typically 0.8V).
Enable Input. The EN pin enables the regulator. When the pin is pulled below the
threshold, the regulator will shut down to an ultra-low current state. A precise threshold
voltage allows the pin to operate as an accurate UVLO. Do not tie EN to V_DD
Supply voltage for the internal LDO. The VIN operating voltage range is from 4.6V to
60V. A ceramic capacitor from V_IN to AGND is required for decoupling. The decoupling
capacitor should be placed as close as possible to the supply pin.
Current Limit Setting. Connect a resistor from this pin to the SW pin node to allow for
accurate current limit sensing programming of the internal low-side power MOSFET.
Internal +5V Linear Regulator: V_DD is the internal supply bus for the IC. Connect to an
external 1 µF bypass capacitor. When V_IN is <5.5V, this regulator operates in drop-out
mode. Connect V_DD to V_IN.
A 5V supply input for the low-side N-channel MOSFET driver circuit, which can be tied
to V_DD externally. A 1 μF ceramic capacitor from PV_DD to PGND is recommended for
decoupling.
Switching Frequency Adjust pin. Connect this pin to V_IN to operate at 680 kHz. Place a
resistor divider network from V_IN to the FREQ pin to program the switching frequency.
 2016 Microchip Technology Inc.
DS20005520A-page 17