MCP6S91 Datasheet, PDF (17/40 Pages) Microchip Technology – Single-Ended, Rail-to-Rail I/O, Low-Gain PGA

MCP6S91/2/3
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP6S91
1
2
—
3
4
5
6
—
7
8
MCP6S92
1
2
3
—
4
5
6
—
7
8
MCP6S93
1
2
3
4
5
6
7
8
9
10
Symbol
V_OUT
CH0
CH1
V_REF
V_SS
CS
SI
SO
SCK
V_DD
Description
Analog Output
Analog Input
Analog Input
External Reference Pin
Negative Power Supply
SPI™ Chip Select
SPI Serial Data Input
SPI Serial Data Output
SPI Clock Input
Positive Power Supply
3.1 Analog Output
The output pin (V_OUT) is a low-impedance voltage
source. The selected gain (G), selected input (CH0,
CH1) and voltage at V_REF determine its value.
3.2 Analog Inputs (CH0, CH1)
The inputs CH0 and CH1 connect to the signal
sources. They are high-impedance CMOS inputs with
low bias currents. The internal MUX selects which one
is amplified to the output.
3.3 External Reference Voltage (V_REF)
The V_REF pin, which is an analog input, should be at a
voltage between V_SS and V_DD (the MCP6S92 has
V_REF tied internally to V_SS). The voltage at this pin
shifts the output voltage.
3.4 Power Supply (V_SS and V_DD)
The Positive Power Supply Pin (V_DD) is 2.5V to 5.5V
higher than the Negative Power Supply Pin (V_SS). For
normal operation, the other pins are at voltages
between V_SS and V_DD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, V_SS is connected to
ground and V_DD is connected to the supply. V_DD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the V_DD pin. These parts can
share a bulk capacitor with analog parts (typically
2.2 µF to 10 µF) within 100 mm of the V_DD pin.
3.5 Digital Inputs
The SPI interface inputs are: Chip Select (CS), Serial
Input (SI) and Serial Clock (SCK). These are Schmitt-
triggered, CMOS logic inputs.
3.6 Digital Output
The MCP6S93 device has a SPI interface Serial Output
(SO) pin. This is a CMOS push-pull output and does
not ever go High-Z. Once the device is deselected (CS
goes high), SO is forced low. This feature supports
daisy-chaining, as explained in Section 5.3 “Daisy-
Chain Configuration”.
 2004 Microchip Technology Inc.
DS21908A-page 17