MCP3550 Datasheet, PDF(17/30 Page) Microchip Technology – Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs

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MCP3550 Datasheet, PDF (17/30 Pages) Microchip Technology – Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs

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5.0 SERIAL INTERFACE

5.1 Overview

Serial communication between the microcontroller and

the MCP3550/1/3 devices is achieved using CS, SCK

and SDO/RDY. There are two modes of operation:

Single Conversion and Continuous Conversion. CS

controls the conversion start. There are 24 bits in the

data word: 22 bits of conversion data and two overflow

bits. The conversion process takes place via the inter-

nal oscillator and the status of this conversion must be

detected. The typical method of communication is

shown in Figure 5-1. The status of the internal conver-

sion is the SDO/RDY pin and is available with CS low.

A High state on SDO/RDY means the device is busy

converting, while a Low state means the conversion is

finished and data is ready for transfer using SCK.

SDO/RDY remains in a high-impedance state when

CS is held high. CS must be low when clocking out the

data using SCK and SDO/RDY.

Bit 22 is Overflow High (OVH) when VIN > VREF â 1 LSB,

OVH toggles to logic â1â, detecting an overflow high in

the analog input voltage.

Bit 23 is Overflow Low (OVL) when VIN < -VREF, OVL

toggles to logic â1â, detecting an overflow low in the

analog input voltage. The state OVH = OVL = â1â is not

defined and should be considered as an interrupt for

the SPI interface meaning erroneous communication.

MCP3550/1/3

Bit 21 to bit 0 represents the output code in 22-bit

binary two's complement. Bit 21 is the sign bit and is

logic â0â when the differential analog input is positive

and logic â1â when the differential analog input is

negative. From Bit 20 to bit 0, the output code is given

MSb first (MSb is bit 20 and LSB is Bit 0). When the

analog input value is comprised between -VREF and

VREF â 1 LSB, the two overflow bits are set to logic â0â.

The relationship between input voltage and output

code is shown in Figure 5-1.

The delta-sigma modulator saturation point for the

differential analog input is located at around Â±112% of

VREF (at room temperature), meaning that the modula-

tor will still give accurate output codes with an over-

range of 12% below or above the reference voltage.

Unlike the usual 22-bit device, the 22-bit output code

will not lock at 0x1FFFFF for positive sign inputs or

0x200000 for negative sign inputs in order to take

advantage of the overrange capabilities of the device.

This can be practical for closed-loop operations, for

instance. In case of an overflow, the output code

becomes a 23-bit two's complement output code,

where the sign bit will be the OVL bit. If an overflow high

or low is detected, OVL (bit 23) becomes the sign bit

(instead of bit 21), the MSb is then bit 21 and the con-

verter can be used as a 23-bit two's complement code

converter, with output code from bits B21 to B0, and

OVL as the sign bit. Figure 5-1 summarizes the output

coding data format with or without overflow high and

low.

SCK

SDO/RDY

READY

21 20 19 18 17

15 14 13 12 11 10 9

HI-Z

76 5 43 21

FIGURE 5-1:

Typical Serial Device Communication and Example Digital Output Codes for Specific

Analog Input Voltages.

DS21950D-page 17

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