HCS370_11 Datasheet, PDF (17/42 Pages) Microchip Technology – KEELOQ® Code Hopping Encoder Four selectable baud rates

FIGURE 5-2: LED OPERATION
SN
LED
VDD > VLOW
TLEDON
TLEDOFF
LED
VDD < VLOW
LEDBL=1
LED
VDD < VLOW
LEDBL=0
5.4 Step-Up Voltage Regulator
To create your own step-up regulator circuit, first decide
on an output voltage. Second, set the VIN resistor
divider to drop it down to 1.2 volts. Keep the sum of the
two resistors around 100 kΩ. Third, put your maximum
load on the output and increase the inductance until
COUT charges from 0 volts to your output voltage in
about 30 ms from the minimum input voltage. Finally,
test over your temperature and input voltage ranges.
The WAIT option will delay RF transmissions until
COUT is charged. This permits a trade off in slower but-
ton response times to save money on cheaper induc-
tors. This can also optimize performance for good
batteries and let response times drift for weak batteries.
Also, this option will indicate failure to reach regulation
voltage after 250 ms by not transmitting and not flash-
ing the LED. If WAIT is disabled, the step-up regulator
still operates and transmissions will always start 30 ms
after a button press.
The SLEEP Output Enable (SOEN) option can be
enabled if S5 is not used. This reconfigures S5 to be an
output high when the HCS370 is sleeping. S5 will be an
output low when a button press wakes it up. One way
to use this option is to save power on the step-up reg-
ulator. The problem is that the VIN resistor divider
makes a DC path through the inductor and diode to dis-
charge the battery. By tying the bottom of the divider to
SLEEP as shown in Figure 2-1, the path is broken
between transmissions.
5.5 Cyclic Redundancy Check (CRC)
The CRC bits are calculated on the 65 previously trans-
mitted bits. These bits contain the 32-bit hopping code,
32-bit fixed code, and VLOW bit. The decoder can use
the CRC bits to check the data integrity before process-
ing starts. The CRC can detect all single bit errors and
66% of double bit errors. The CRC is computed as fol-
lows:
HCS370
EQUATION 5-1: CRC Calculation
CRC[1]_{n + 1} = CRC[0]_n ⊕ Di_n
and
CRC[0]_{n + 1} = (CRC[0]_n ⊕ Di_n) ⊕ CRC[1]_n
with
CRC[1, 0]₀ = 0
and Di_n the nth transmission bit 0 <= n <= 64
5.6 Button Queue Information
(QUEUE)
The queuing or repeated pressing of the same buttons
can be handled in two ways on the HCS370. This is
controlled with the Queue Counter Enable (QUEN)
configuration option. This option can be different for
Encoder 1 and Encoder 2.
When the QUEN option is disabled, the device will reg-
ister up to two sequential button presses. In this case,
the device will complete the minimum code words
selected with the MTX option before the second code
word is calculated and transmitted. The code word will
be 67 bits in this case, with no additional queue bits
transmitted.
If the QUEN option is enabled, the queue bits are
added to the standard code word. The queue bits are a
2-bit counter that does not wrap. The counter value
starts at 00₂ and is incremented if a button is pushed
within 2 seconds from the start of the previous button
press. The current code word is terminated when a but-
ton is queued. This allows additional functionality for
double or triple button presses.
FIGURE 5-3:
SN
CODE WORD COMPLETION
WITH QUEN SETTINGS
MTX = 01₂, WAKE > 00₂
QUEN = Disabled
DATA WAKE-UP CODE1
CODE1
WAKE-UP CODE2
CODE2
QUEN = Enabled
DATA WAKE-UP CODE1 00
WAKE-UP CODE2 01 CODE2 01
6.0 PROGRAMMING
SPECIFICATIONS
Refer to the “HCS370 Programming Specifications”
document (DS41157) in Microchip Literature.
2011 Microchip Technology Inc.
DS41111E-page 17