PIC12F609 Datasheet, PDF (16/168 Pages) Microchip Technology – 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

PIC12F609/615/12HV609/615
TABLE 2-4: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 22, 101
81h OPTION_REG GPPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 16, 101
82h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 22, 101
83h STATUS
IRP⁽¹⁾
RP1⁽¹⁾
RP0
TO
PD
Z
DC
C
0001 1xxx 15, 101
84h FSR
85h TRISIO
Indirect Data Memory Address Pointer
—
—
TRISIO5 TRISIO4 TRISIO3⁽⁴⁾ TRISIO2
TRISIO1
xxxx xxxx 22, 101
TRISIO0 --11 1111 31, 101
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah PCLATH
8Bh INTCON
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 22, 101
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF⁽³⁾ 0000 0000 17, 101
8Ch PIE1
—
ADIE
CCP1IE
—
CMIE
—
TMR2IE TMR1IE -00- 0-00 18, 101
8Dh
—
Unimplemented
—
—
8Eh PCON
—
—
—
—
—
—
POR
BOR ---- --qq 20, 101
8Fh
—
Unimplemented
—
—
90h OSCTUNE
—
—
—
TUN4
TUN3
TUN2
TUN1
TUN0 ---0 0000 29, 101
91h
—
Unimplemented
—
—
92h PR2
Timer2 Module Period Register
1111 1111 51, 101
93h APFCON
—
—
—
T1GSEL
—
—
P1BSEL P1ASEL ---0 --00 18, 101
94h
—
Unimplemented
—
—
95h WPU⁽²⁾
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0 --11 -111 34, 101
96h IOC
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0 --00 0000 34, 101
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh ADRESL
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
xxxx xxxx 71, 101
9Fh ANSEL
—
ADCS2 ADCS1 ADCS0
ANS3
ANS2
ANS1
ANS0 -000 1111 33, 101
Legend:
Note 1:
2:
3:
4:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
TRISIO3 always reads as ‘1’ since it is an input only pin.
DS41302A-page 14
Preliminary
© 2006 Microchip Technology Inc.