MIC24052 Datasheet, PDF (16/34 Pages) Micrel Semiconductor – 12V, 6A High-Efficiency Buck Regulator

MIC24052
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Pin Number Pin Name
Description
1
2, 5, 6, 7, 8, 21
3
4, 9, 10, 11, 12
13,14,15,
16,17,18,19
20
22
23
24
25
26
27
28
PV_DD
PGND
NC
SW
PV_IN
BST
CS
SGND
FB
PG
EN
V_IN
V_DD
5V Internal Linear Regulator output. PV_DD supply is the power MOSFET gate drive
supply voltage and created by internal LDO from V_IN. When V_IN < +5.5V, PV_DD should
be tied to PV_IN pins. A 2.2 µF ceramic capacitor from the PV_DD pin to PGND (Pin 2)
must be place next to the IC.
Power Ground. PGND is the ground path for the MIC24052 buck converter power
stage. The PGND pins connect to the low-side N-Channel internal MOSFET gate
drive supply ground, the sources of the MOSFETs, the negative terminals of input
capacitors, and the negative terminals of output capacitors. The loop for the power
ground should be as small as possible and separate from the signal ground (SGND)
loop.
No connect.
Switch Node output. Internal connection for the high-side MOSFET source and
low-side MOSFET drain. Due to the high-speed switching on this pin, the SW pin
should be routed away from sensitive nodes.
High-Side N-internal MOSFET Drain Connection input. The PV_IN operating voltage
range is from 4.5V to 19V. Input capacitors between the PV_IN pins and the Power
Ground (PGND) are required to keep the connection short.
Boost output. Bootstrapped voltage to the high-side N-channel MOSFET driver. A
Schottky diode is connected between the PV_DD pin and the BST pin. A boost
capacitor of 0.1 μF is connected between the BST pin and the SW pin. Adding a small
resistor at the BST pin can slow down the turn-on time of high-side N-Channel
MOSFETs.
Current Sense input. The CS pin senses current by monitoring the voltage across the
low-side MOSFET during the OFF-time. The current sensing is necessary for
short-circuit protection and zero crossing detection. In order to sense the current
accurately, connect the low-side MOSFET drain to SW using a Kelvin connection. The
CS pin is also the high-side MOSFET’s output driver return.
Signal Ground. SGND must be connected directly to the ground planes. Do not route
the SGND pin to the PGND Pad on the top layer (see PCB Layout Recommendations
for details).
Feedback input. Input to the transconductance amplifier of the control loop. The FB
pin is regulated to 0.8V. A resistor divider connecting the feedback to the output is
used to adjust the desired output voltage.
Power Good output. Open drain output. The PG pin is externally tied with a resistor to
V_DD. A high output is asserted when V_OUT > 92% of nominal.
Enable input. A logic level control of the output. The EN pin is CMOS-compatible.
Logic high = enable, logic low = shutdown. In the off state, supply current of the device
is greatly reduced (typically 5 µA). The EN pin should not be left floating.
Power Supply Voltage input. Requires bypass capacitor to SGND.
5V Internal Linear Regulator output. V_DD supply is the supply bus for the IC control
circuit. V_DD is created by internal LDO from V_IN. When V_IN < +5.5V, V_DD should be
tied to PV_IN pins. A 1 µF ceramic capacitor from the V_DD pin to SGND pins must be
place next to the IC.
DS20005659A-page 16
 2016 Microchip Technology Inc.