MIC2125 Datasheet, PDF (16/34 Pages) Microchip Technology – 28V Synchronous Buck Controllers Featuring Adaptive ON-Time Control

MIC2125/6
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Pin Number
Symbol
Description
1
V_DD Internal Linear regulator output. Connect a 4.7 μF ceramic capacitor from V_DD to
A_GND for decoupling. In the applications where V_IN < +5.5V, V_DD should be tied to
V_IN to by-pass the linear regulator.
2
P_VDD 5V supply input for the low-side N-channel MOSFET driver, which can be tied to
V_DD externally. A 4.7 μF ceramic capacitor from P_VDD to P_GND is recommended for
decoupling.
3
I_LIM
Current limit setting input. Connect a resistor from SW to I_LIM to set the overcurrent
threshold for the converter.
4
DL
Low-side gate driver output. The DL driving voltage swings from ground to V_DD.
5
P_GND Power ground. P_GND is the return path for the low side gate driver. Connect P_GND
pin to the source of low-side N-Channel external MOSFET.
6
FREQ Switching frequency adjust input. Connect FREQ to the mid-point of an external
resistor divider from V_IN to GND to program the switching frequency. Tie to V_IN to
operate at 750 kHz frequency.
7
DH High-side gate driver output. The DH driving voltage is floating on the switch node
voltage (V_SW).
8
SW Switch node and current-sense input. Connect the SW pin to the switch node of the
buck converter. The SW pin also senses the current by monitoring the voltage
across the low-side MOSFET during OFF time. In order to sense the current
accurately, connect the low-side MOSFET drain to the SW pin using a Kelvin
connection.
9
BST Bootstrap Capacitor Input. Connect a ceramic capacitor with a minimum value of
0.1 μF from BST to SW.
10
OVP Output Overvoltage Protection Input. Connect to the mid-point of an external
resistive divider from the V_OUT to GND to program overvoltage limit. Connect to
A_GND if the output overvoltage protection is not required.
11
NC No connect.
12
A_GND Analog Ground. Connect A_GND to the exposed pad.
13
FB
Feedback input. Input to the transconductance amplifier of the control loop. The FB
pin is regulated to 0.6V. A resistor divider connecting the feedback to the output is
used to set the desired output voltage.
14
PG
Open-drain Power good output. Pull-up with an external pull-up resistor to V_DD or to
an external power rail.
15
EN Enable input. A logic signal to enable or disable the buck converter operation.
Logic-high enables the device; logic-low shuts down the regulator. In disable mode,
the V_DD supply current for the device is minimized to 0.1 µA typically. Do not pull-up
EN pin to V_DD/P_VDD.
16
V_IN
Supply voltage input. The V_IN operating voltage range is from 4.5V to 28V. A 1 μF
ceramic capacitor from V_IN to A_GND is required for decoupling.
17
EP
Exposed Pad. Connect the exposed pad to the A_GND copper plane to improve the
thermal performance.
DS20005459B-page 16
 2015 Microchip Technology Inc.