TC1303B Datasheet, PDF (15/30 Pages) Microchip Technology – 500 mA Synchronous Buck Regulator, + 300 mA LDO with Power-Good Output

TC1303B
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Pin No.
Name
Function
1
SHDN2 Active Low Shutdown Input for LDO Output Pin
2
V_IN2 Analog Input Supply Voltage Pin
3
V_OUT2 LDO Output Voltage Pin
4
PG
Power-good Output Pin
5
A_GND Analog Ground Pin
6
V_FB / V_OUT1 Buck Feedback Voltage (Adjustable Version) / Buck Output Voltage (Fixed Version) Pin
7
SHDN1 Active Low Shutdown Input for Buck Regulator Output Pin
8
V_IN1 Buck Regulator Input Voltage Pin
9
L_X
Buck Inductor Output Pin
10
P_GND Power Ground Pin
EP
Exposed For the DFN package, the center exposed pad is a thermal path to remove heat from the
Pad device. Electrically this pad is at ground potential and should be connected to A_GND.
3.1 LDO Shutdown Input Pin (SHDN2)
3.7 Buck Regulator Shutdown Input
SHDN2 is a logic level input used to turn the LDO Reg-
ulator on and off. A logic high (> 45% of V_IN), will enable
the regulator output. A logic low (< 15% of V_IN) will
ensure that the output is turned off.
3.2 LDO Input Voltage Pin (V_IN2)
V_IN2 is a LDO power input supply pin. Connect variable
input voltage source to V_IN2. Connect V_IN1 and V_IN2
together with board traces as short as possible. V_IN2
provides the input voltage for the LDO regulator. An
additional capacitor can be added to lower the LDO
regulator input ripple voltage.
3.3 LDO Output Voltage Pin (V_OUT2)
V_OUT2 is a regulated LDO output voltage pin. Connect
a 1 µF or larger capacitor to V_OUT2 and A_GND for proper
operation.
3.4 Power-Good Output Pin (PG)
PG is an output level indicating that V_OUT2 (LDO) is
within 94% of regulation. The PG output is configured
as a push-pull for the TC1303B.
3.5 Analog Ground Pin (A_GND)
A_GND is the analog ground connection. Tie A_GND to the
analog portion of the ground plane (A_GND). See the
physical layout information in Section 5.0 “Application
Circuits/Issues” for grounding recommendations.
Pin (SHDN1)
SHDN1 is a logic level input used to turn the buck
regulator on and off. A logic-high (> 45% of V_IN), will
enable the regulator output. A logic-low (< 15% of V_IN)
will ensure that the output is turned off.
3.8 Buck Regulator Input Voltage Pin
(V_IN1)
V_IN1 is the buck regulator power input supply pin.
Connect a variable input voltage source to V_IN1.
Connect V_IN1 and V_IN2 together with board traces as
short as possible.
3.9 Buck Inductor Output Pin (L_X)
Connect L_X directly to the buck inductor. This pin
carries large signal-level current; all connections
should be made as short as possible.
3.10 Power Ground Pin (P_GND)
Connect all large-signal level ground returns to P_GND.
These large-signal, level ground traces should have a
small loop area and length to prevent coupling of
switching noise to sensitive traces. Please see the
physical layout information supplied in Section 5.0
“Application Circuits/Issues” for grounding
recommendations.
3.11 Exposed Pad (EP)
3.6 Buck Regulator Output Sense Pin
(V_FB/V_OUT1)
For the DFN package, connect the EP to A_GND with
vias into the A_GND plane.
For V_OUT1 adjustable output voltage options, connect
the center of the output voltage divider to the V_FB pin.
For fixed-output voltage options, connect the output of
the buck regulator to this pin (V_OUT1).
© 2005 Microchip Technology Inc.
DS21949A-page 15