SST25WF020A_14 Datasheet, PDF (15/39 Pages) Microchip Technology – 2 Mbit 1.8V SPI Serial Flash

SST25WF020A
5.10 Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new val-
ues to the BP0, BP1, TB, and BPL bits of the status reg-
ister. CE# must be driven low before the command
sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed.
Poll the BUSY bit in the Software Status register, or
wait T_WRSR, for the completion of the internal self-timed
Write-Status-Register cycle. See Figure 5-10 for
WREN and WRSR instruction sequences and Figure
7.0 for the WRSR flow chart.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to ‘1’. When
the WP# is low, the BPL bit can only be set from ‘0’ to
‘1’ to lock-down the status register, but cannot be reset
from ‘1’ to ‘0’. When WP# is high, the lock-down func-
tion of the BPL bit is disabled and the BPL, BP0, BP1,
and TB bits in the status register can all be changed. As
long as BPL bit is set to ‘0’ or WP# pin is driven high
(V_IH) prior to the low-to-high transition of the CE# pin at
the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL
bit to ‘1’ to lock down the status register as well as alter-
ing the BP0, BP1, and TB bits at the same time. See
Table 4-1 for a summary description of WP# and BPL
functions.
FIGURE 5-10:
CE#
WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
MODE 3
SCK MODE 0
0 1 2345 6 7
SI
06
MSB
SO
MODE 3
MODE 0
0 1 2345 6 78
10 11 12 13 14 15
01
MSB
HIGH IMPEDANCE
STATUS
REGISTER IN
76543210
MSB
2513 F20.0
 2014 Microchip Technology Inc.
DS20005139E-page 15