DSPIC33FJ06GS202-EMM Datasheet, PDF (15/20 Pages) Microchip Technology – dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Family Silicon Errata and Data Sheet Clarification

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
38. Module: CPU
When a previous DISI instruction is active (i.e.,
the DISICNT register is non-zero), and the value of
the DISICNT register is updated manually, the
DISICNT register freezes and disables interrupts
permanently.
Work around
Avoid updating the DISICNT register manually.
Instead, use the DISI #n instruction with the
required value for ‘n’.
Affected Silicon Revisions
A2 A3 A4
XXX
39. Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions
A2 A3 A4
XXX
40. Module: UART
When using UTXISEL = 01 (interrupt when last
character is shifted out of the Transmit Shift
Register) and the final character is being shifted
out through the Transmit Shift Register, the
Transmit (TX) interrupt may occur before the final
bit is shifted out.
Work around
If it is critical that the interrupt processing occur
only when all transmit operations are complete.
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
Affected Silicon Revisions
A2 A3 A4
XXX
41. Module: JTAG
JTAG Flash programming is not supported.
Work around
None.
Affected Silicon Revisions
A2 A3 A4
XXX
42. Module: PWM
When operating in Edge-Aligned Complimentary
mode, if the duty cycle (PDCx) becomes less than
the alternate dead time (ALTDTRx), the dead time
on the PWMs will become 0.
Work around
Ensure that the duty cycle (PDCx) always meets
the following condition: PDCx > (ALTDTRx – 1).
Affected Silicon Revisions
A2 A3 A4
XXX
43. Module: PWM
If the PWM Clock Divider Select register, PTCON2, is
not equal to zero, the PWM module may or may
not initialize from an override state
(IOCONxbits.OVRENH = 1 or
IOCONxbits.OVRENL = 1).
Work around
When configuring the Override Enable bits
(OVRENL/OVRENH) in the PWMx I/O Control
register, IOCONx, set these bits implicitly via word
format and not explicitly via bit format.
For example:
IOCONx = IOCONx & 0xFCFF;
Affected Silicon Revisions
A2 A3 A4
XXX
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DS80439M-page 15