DSPIC30F2010-30I Datasheet, PDF (15/203 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F2010
2.4 DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/sub-
tracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform inher-
ent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
1. Fractional or integer DSP multiply (IF).
2. Signed or unsigned DSP multiply (US).
3. Conventional or convergent rounding (RND).
4. Automatic saturation on/off for ACCA (SATA).
5. Automatic saturation on/off for ACCB (SATB).
6. Automatic saturation on/off for writes to data
memory (SATDW).
7. Accumulator Saturation mode selection
(ACCSAT).
Note: For CORCON layout, see Table 3-3.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2: DSP INSTRUCTION SUMMARY
Instruction
Algebraic Operation
ACC WB?
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY.N
MSC
A=0
Yes
A = (x – y)²
No
A = A + (x – y)²
No
A = A + (x * y)
Yes
A = A + x²
No
No change in A
Yes
A=x*y
No
A=–x*y
No
A=A–x*y
Yes
© 2006 Microchip Technology Inc.
DS70118G-page 13