TC7109 Datasheet, PDF (14/30 Pages) TelCom Semiconductor, Inc – 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

TC7109/A
Integrator Output
Zero Crossing Occurs
Zero Crossing Detected
Internal Clock
Internal Latch
Status Output
Mode Input
UART
Internal Mode ^Norm
Send Input (UART TBRE)
CE/LOAD Output (UART TBRL)
HBEN
High Byte Data
LBEN
Send
Sensed
Send
Sensed
Data Valid
Send
Sensed
Low Byte Data
= Don't Care
Data Valid
= Three-State High-Impedance
Terminates
UART Mode
FIGURE 3-8:
TC7109A Handshake – Typical UART Interface Timing
Positive Transiton causes
Entry into UART Mode
Internal Clock
Internal Latch
Status Output
Mode Input
UART
Norm
Internal Mode
Send Input
CE/LOAD as Output
HBEN
High Byte Data
LBEN
Low Byte Data
Status Output unchanged
in UART Mode
Zero Crossing Occurs
Zero Crossing Detected
Latch Pulse inhibited in UART Mode
Send
Sensed
DE Phase III
Send
Sensed
Send
Sensed
Terminates
UART Mode
Data Valid
Data Valid
= Don't Care
=
Three-State
High-Impedance
=
Three-State
with Pull-up
FIGURE 3-9:
TC7109A Handshake Triggered by Mode Input
DS21456C-page 14
© 2006 Microchip Technology Inc.